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Searched refs:ArgLocs (Results 1 – 19 of 19) sorted by relevance

/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFISelLowering.cpp204 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
205 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); in LowerFormalArguments()
208 for (auto &VA : ArgLocs) { in LowerFormalArguments()
280 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall() local
281 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); in LowerCall()
310 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCall()
311 CCValAssign &VA = ArgLocs[i]; in LowerCall()
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430ISelLowering.cpp284 SmallVectorImpl<CCValAssign> &ArgLocs, in AnalyzeArguments() argument
338 SmallVectorImpl<CCValAssign>::iterator B = ArgLocs.begin() + FirstVal; in AnalyzeArguments()
441 SmallVector<CCValAssign, 16> ArgLocs; in LowerCCCArguments() local
442 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCCCArguments()
444 AnalyzeArguments(CCInfo, ArgLocs, Ins); in LowerCCCArguments()
452 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCCCArguments()
453 CCValAssign &VA = ArgLocs[i]; in LowerCCCArguments()
587 SmallVector<CCValAssign, 16> ArgLocs; in LowerCCCCallTo() local
588 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCCCCallTo()
590 AnalyzeArguments(CCInfo, ArgLocs, Outs); in LowerCCCCallTo()
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/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp352 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments_32() local
353 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments_32()
360 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) { in LowerFormalArguments_32()
361 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments_32()
384 CCValAssign &NextVA = ArgLocs[++i]; in LowerFormalArguments_32()
553 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments_64() local
554 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments_64()
561 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerFormalArguments_64()
562 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments_64()
702 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall_32() local
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/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp483 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall() local
484 HexagonCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCall()
502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCall()
503 CCValAssign &VA = ArgLocs[i]; in LowerCall()
523 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCall()
524 CCValAssign &VA = ArgLocs[i]; in LowerCall()
872 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
873 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments()
887 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerFormalArguments()
888 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments()
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreISelLowering.cpp1137 SmallVector<CCValAssign, 16> ArgLocs; in LowerCCCCallTo() local
1138 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCCCCallTo()
1165 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCCCCallTo()
1166 CCValAssign &VA = ArgLocs[i]; in LowerCCCCallTo()
1303 SmallVector<CCValAssign, 16> ArgLocs; in LowerCCCArguments() local
1304 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCCCArguments()
1328 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCCCArguments()
1330 CCValAssign &VA = ArgLocs[i]; in LowerCCCArguments()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCFastISel.cpp1273 SmallVector<CCValAssign, 16> ArgLocs; in processCallArgs() local
1274 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, *Context); in processCallArgs()
1283 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { in processCallArgs()
1284 CCValAssign &VA = ArgLocs[I]; in processCallArgs()
1321 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { in processCallArgs()
1322 CCValAssign &VA = ArgLocs[I]; in processCallArgs()
HDPPCISelLowering.cpp2814 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments_32SVR4() local
2815 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments_32SVR4()
2824 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerFormalArguments_32SVR4()
2825 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments_32SVR4()
4512 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall_32SVR4() local
4513 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCall_32SVR4()
4594 for (unsigned i = 0, j = 0, e = ArgLocs.size(); in LowerCall_32SVR4()
4597 CCValAssign &VA = ArgLocs[i]; in LowerCall_32SVR4()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMFastISel.cpp1890 SmallVector<CCValAssign, 16> ArgLocs; in ProcessCallArgs() local
1891 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context); in ProcessCallArgs()
1897 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in ProcessCallArgs()
1898 CCValAssign &VA = ArgLocs[i]; in ProcessCallArgs()
1912 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) in ProcessCallArgs()
1947 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in ProcessCallArgs()
1948 CCValAssign &VA = ArgLocs[i]; in ProcessCallArgs()
1996 CCValAssign &NextVA = ArgLocs[++i]; in ProcessCallArgs()
HDARMISelLowering.cpp1529 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall() local
1530 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCall()
1557 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); in LowerCall()
1560 CCValAssign &VA = ArgLocs[i]; in LowerCall()
1592 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); in LowerCall()
1594 VA = ArgLocs[++i]; // skip ahead to next loc in LowerCall()
1597 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); in LowerCall()
1605 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], in LowerCall()
2114 SmallVector<CCValAssign, 16> ArgLocs; in IsEligibleForTailCallOptimization() local
2115 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs, in IsEligibleForTailCallOptimization()
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/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsFastISel.cpp1080 SmallVector<CCValAssign, 16> ArgLocs; in processCallArgs() local
1081 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context); in processCallArgs()
1092 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in processCallArgs()
1093 CCValAssign &VA = ArgLocs[i]; in processCallArgs()
HDMipsISelLowering.cpp2579 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall() local
2581 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), in LowerCall()
2626 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCall()
2628 CCValAssign &VA = ArgLocs[i]; in LowerCall()
2945 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
2946 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments()
2959 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerFormalArguments()
2960 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments()
3047 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerFormalArguments()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZISelLowering.cpp880 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
881 SystemZCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); in LowerFormalArguments()
886 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { in LowerFormalArguments()
888 CCValAssign &VA = ArgLocs[I]; in LowerFormalArguments()
994 SmallVectorImpl<CCValAssign> &ArgLocs) { in canUseSiblingCall() argument
997 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { in canUseSiblingCall()
998 CCValAssign &VA = ArgLocs[I]; in canUseSiblingCall()
1033 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall() local
1034 SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); in LowerCall()
1039 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs)) in LowerCall()
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/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIISelLowering.cpp547 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
548 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments()
606 CCValAssign &VA = ArgLocs[ArgIdx++]; in LowerFormalArguments()
663 Reg = ArgLocs[ArgIdx++].getLocReg(); in LowerFormalArguments()
HDR600ISelLowering.cpp1633 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
1634 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments()
1646 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments()
1685 unsigned ValBase = ArgLocs[In.getOrigArgIndex()].getLocMemOffset(); in LowerFormalArguments()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp2075 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
2076 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments()
2110 assert(ArgLocs.size() == Ins.size()); in LowerFormalArguments()
2112 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerFormalArguments()
2113 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments()
2451 SmallVector<CCValAssign, 16> ArgLocs; in isEligibleForTailCallOptimization() local
2452 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs, in isEligibleForTailCallOptimization()
2456 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) in isEligibleForTailCallOptimization()
2457 if (!ArgLocs[i].isRegLoc()) in isEligibleForTailCallOptimization()
2495 SmallVector<CCValAssign, 16> ArgLocs; in isEligibleForTailCallOptimization() local
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HDAArch64FastISel.cpp2944 SmallVector<CCValAssign, 16> ArgLocs; in processCallArgs() local
2945 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context); in processCallArgs()
2957 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in processCallArgs()
2958 CCValAssign &VA = ArgLocs[i]; in processCallArgs()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86FastISel.cpp2917 SmallVector<CCValAssign, 16> ArgLocs; in fastLowerCall() local
2918 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, CLI.RetTy->getContext()); in fastLowerCall()
2936 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in fastLowerCall()
2937 CCValAssign const &VA = ArgLocs[i]; in fastLowerCall()
HDX86ISelLowering.cpp2443 SmallVector<CCValAssign, 16> ArgLocs; in LowerFormalArguments() local
2444 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext()); in LowerFormalArguments()
2454 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerFormalArguments()
2455 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments()
2530 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerFormalArguments()
2885 SmallVector<CCValAssign, 16> ArgLocs; in LowerCall() local
2886 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext()); in LowerCall()
2925 if (!ArgLocs.back().isMemLoc()) in LowerCall()
2928 if (ArgLocs.back().getLocMemOffset() != 0) in LowerCall()
2950 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { in LowerCall()
[all …]
/NextBSD/contrib/llvm/tools/clang/lib/Sema/
HDSemaTemplateInstantiateDecl.cpp2495 SmallVector<TemplateArgumentLoc, 4> ArgLocs; in VisitClassTemplateSpecializationDecl() local
2497 ArgLocs.push_back(Loc.getArgLoc(I)); in VisitClassTemplateSpecializationDecl()
2498 if (SemaRef.Subst(ArgLocs.data(), ArgLocs.size(), in VisitClassTemplateSpecializationDecl()