1 /* $NetBSD: vrip.c,v 1.39 2021/08/07 16:18:54 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 1999, 2002
5 * Shin Takemura and PocketBSD Project. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the project nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 */
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: vrip.c,v 1.39 2021/08/07 16:18:54 thorpej Exp $");
35
36 #include "opt_vr41xx.h"
37 #include "opt_tx39xx.h"
38
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/device.h>
42 #include <sys/reboot.h>
43
44 #include <machine/cpu.h>
45 #include <machine/bus.h>
46 #include <machine/autoconf.h>
47 #include <machine/platid.h>
48 #include <machine/platid_mask.h>
49
50 #include <hpcmips/vr/vr.h>
51 #include <hpcmips/vr/vrcpudef.h>
52 #include <hpcmips/vr/vripunit.h>
53 #include <hpcmips/vr/vripif.h>
54 #include <hpcmips/vr/vripreg.h>
55 #include <hpcmips/vr/vripvar.h>
56 #include <hpcmips/vr/icureg.h>
57 #include <hpcmips/vr/cmureg.h>
58 #include "locators.h"
59
60 #ifdef VRIP_DEBUG
61 #define DPRINTF_ENABLE
62 #define DPRINTF_DEBUG vrip_debug
63 #endif
64 #define USE_HPC_DPRINTF
65 #include <machine/debug.h>
66
67 #ifdef VRIP_DEBUG
68 #define DBG_BIT_PRINT(reg) if (vrip_debug) dbg_bit_print(reg);
69 #define DUMP_LEVEL2MASK(sc,arg) if (vrip_debug) __vrip_dump_level2mask(sc,arg)
70 #else
71 #define DBG_BIT_PRINT(arg)
72 #define DUMP_LEVEL2MASK(sc,arg)
73 #endif
74
75 #define VALID_UNIT(sc, unit) (0 <= (unit) && (unit) < (sc)->sc_nunits)
76
77 #ifdef SINGLE_VRIP_BASE
78 int vripmatch(device_t, cfdata_t, void *);
79 void vripattach(device_t, device_t, void *);
80 #endif
81 int vrip_print(void *, const char *);
82 int vrip_search(device_t, cfdata_t, const int *, void *);
83 int vrip_intr(void *, vaddr_t, u_int32_t);
84
85 int __vrip_power(vrip_chipset_tag_t, int, int);
86 vrip_intr_handle_t __vrip_intr_establish(vrip_chipset_tag_t, int, int,
87 int, int(*)(void*), void*);
88 void __vrip_intr_disestablish(vrip_chipset_tag_t, vrip_intr_handle_t);
89 void __vrip_intr_setmask1(vrip_chipset_tag_t, vrip_intr_handle_t, int);
90 void __vrip_intr_setmask2(vrip_chipset_tag_t, vrip_intr_handle_t,
91 u_int32_t, int);
92 void __vrip_intr_getstatus2(vrip_chipset_tag_t, vrip_intr_handle_t,
93 u_int32_t*);
94 void __vrip_register_cmu(vrip_chipset_tag_t, vrcmu_chipset_tag_t);
95 void __vrip_register_gpio(vrip_chipset_tag_t, hpcio_chip_t);
96 void __vrip_register_dmaau(vrip_chipset_tag_t, vrdmaau_chipset_tag_t);
97 void __vrip_register_dcu(vrip_chipset_tag_t, vrdcu_chipset_tag_t);
98 void __vrip_dump_level2mask(vrip_chipset_tag_t, void *);
99
100 struct vrip_softc *the_vrip_sc = NULL;
101
102 static const struct vrip_chipset_tag vrip_chipset_methods = {
103 .vc_power = __vrip_power,
104 .vc_intr_establish = __vrip_intr_establish,
105 .vc_intr_disestablish = __vrip_intr_disestablish,
106 .vc_intr_setmask1 = __vrip_intr_setmask1,
107 .vc_intr_setmask2 = __vrip_intr_setmask2,
108 .vc_intr_getstatus2 = __vrip_intr_getstatus2,
109 .vc_register_cmu = __vrip_register_cmu,
110 .vc_register_gpio = __vrip_register_gpio,
111 .vc_register_dmaau = __vrip_register_dmaau,
112 .vc_register_dcu = __vrip_register_dcu,
113 };
114
115 #ifdef SINGLE_VRIP_BASE
116 CFATTACH_DECL_NEW(vrip, sizeof(struct vrip_softc),
117 vripmatch, vripattach, NULL, NULL);
118
119 static const struct vrip_unit vrip_units[] = {
120 [VRIP_UNIT_PMU] = { "pmu",
121 { VRIP_INTR_POWER, VRIP_INTR_BAT, }, },
122 [VRIP_UNIT_RTC] = { "rtc",
123 { VRIP_INTR_RTCL1, }, },
124 [VRIP_UNIT_PIU] = { "piu",
125 { VRIP_INTR_PIU, },
126 CMUMASK_PIU,
127 ICUPIUINT_REG_W, MPIUINT_REG_W },
128 [VRIP_UNIT_KIU] = { "kiu",
129 { VRIP_INTR_KIU, },
130 CMUMASK_KIU,
131 KIUINT_REG_W, MKIUINT_REG_W },
132 [VRIP_UNIT_SIU] = { "siu",
133 { VRIP_INTR_SIU, }, },
134 [VRIP_UNIT_GIU] = { "giu",
135 { VRIP_INTR_GIU, },
136 0,
137 GIUINT_L_REG_W,MGIUINT_L_REG_W,
138 GIUINT_H_REG_W, MGIUINT_H_REG_W },
139 [VRIP_UNIT_LED] = { "led",
140 { VRIP_INTR_LED, }, },
141 [VRIP_UNIT_AIU] = { "aiu",
142 { VRIP_INTR_AIU, },
143 CMUMASK_AIU,
144 AIUINT_REG_W, MAIUINT_REG_W },
145 [VRIP_UNIT_FIR] = { "fir",
146 { VRIP_INTR_FIR, },
147 CMUMASK_FIR,
148 FIRINT_REG_W, MFIRINT_REG_W },
149 [VRIP_UNIT_DSIU]= { "dsiu",
150 { VRIP_INTR_DSIU, },
151 CMUMASK_DSIU,
152 DSIUINT_REG_W, MDSIUINT_REG_W },
153 [VRIP_UNIT_PCIU]= { "pciu",
154 { VRIP_INTR_PCI, },
155 CMUMASK_PCIU,
156 PCIINT_REG_W, MPCIINT_REG_W },
157 [VRIP_UNIT_SCU] = { "scu",
158 { VRIP_INTR_SCU, },
159 0,
160 SCUINT_REG_W, MSCUINT_REG_W },
161 [VRIP_UNIT_CSI] = { "csi",
162 { VRIP_INTR_CSI, },
163 CMUMASK_CSI,
164 CSIINT_REG_W, MCSIINT_REG_W },
165 [VRIP_UNIT_BCU] = { "bcu",
166 { VRIP_INTR_BCU, },
167 0,
168 BCUINT_REG_W, MBCUINT_REG_W },
169 };
170
171 void
vripattach(device_t parent,device_t self,void * aux)172 vripattach(device_t parent, device_t self, void *aux)
173 {
174 struct vrip_softc *sc = device_private(self);
175
176 printf("\n");
177
178 sc->sc_units = vrip_units;
179 sc->sc_nunits = sizeof(vrip_units)/sizeof(struct vrip_unit);
180 sc->sc_icu_addr = VRIP_ICU_ADDR;
181 sc->sc_sysint2 = SYSINT2_REG_W;
182 sc->sc_msysint2 = MSYSINT2_REG_W;
183
184 vripattach_common(parent, self, aux);
185 }
186 #endif /* SINGLE_VRIP_BASE */
187
188 int
vripmatch(device_t parent,cfdata_t match,void * aux)189 vripmatch(device_t parent, cfdata_t match, void *aux)
190 {
191 struct mainbus_attach_args *ma = aux;
192
193 #if defined(SINGLE_VRIP_BASE) && defined(TX39XX)
194 if (!platid_match(&platid, &platid_mask_CPU_MIPS_VR_41XX))
195 return (0);
196 #endif /* SINGLE_VRIP_BASE && TX39XX */
197 if (strcmp(ma->ma_name, match->cf_name))
198 return (0);
199
200 return (1);
201 }
202
203 void
vripattach_common(device_t parent,device_t self,void * aux)204 vripattach_common(device_t parent, device_t self, void *aux)
205 {
206 struct mainbus_attach_args *ma = aux;
207 struct vrip_softc *sc = device_private(self);
208
209 sc->sc_chipset = vrip_chipset_methods; /* structure assignment */
210 sc->sc_chipset.vc_sc = sc;
211
212 #ifdef DIAGNOSTIC
213 if (sc->sc_icu_addr == 0 ||
214 sc->sc_sysint2 == 0 ||
215 sc->sc_msysint2 == 0)
216 panic("vripattach: missing register info.");
217 #endif /* DIAGNOSTIC */
218
219 /*
220 * Map ICU (Interrupt Control Unit) register space.
221 */
222 sc->sc_iot = ma->ma_iot;
223 if (bus_space_map(sc->sc_iot, sc->sc_icu_addr,
224 0x20 /*XXX lower area only*/,
225 0, /* no flags */
226 &sc->sc_ioh)) {
227 printf("vripattach: can't map ICU register.\n");
228 return;
229 }
230
231 /*
232 * Disable all Level 1 interrupts.
233 */
234 sc->sc_intrmask = 0;
235 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT1_REG_W, 0x0000);
236 bus_space_write_2(sc->sc_iot, sc->sc_ioh, sc->sc_msysint2, 0x0000);
237 /*
238 * Level 1 interrupts are redirected to HwInt0
239 */
240 vr_intr_establish(VR_INTR0, vrip_intr, sc);
241 the_vrip_sc = sc;
242 /*
243 * Attach each devices
244 * GIU CMU DMAAU DCU interface interface is used by other system
245 * device. so attach first
246 */
247 sc->sc_pri = 2;
248 config_search(self, NULL,
249 CFARGS(.search = vrip_search));
250
251 /* Other system devices. */
252 sc->sc_pri = 1;
253 config_search(self, NULL,
254 CFARGS(.search = vrip_search));
255 }
256
257 int
vrip_print(void * aux,const char * hoge)258 vrip_print(void *aux, const char *hoge)
259 {
260 struct vrip_attach_args *va = (struct vrip_attach_args*)aux;
261 bus_addr_t endaddr, mask;
262
263 if (va->va_addr != VRIPIFCF_ADDR_DEFAULT)
264 aprint_normal(" addr 0x%08lx", va->va_addr);
265 if (va->va_size != VRIPIFCF_SIZE_DEFAULT) {
266 endaddr = (va->va_addr + va->va_size - 1);
267 mask = ((va->va_addr ^ endaddr) & 0xff0000) ? 0xffffff:0xffff;
268 aprint_normal("-%04lx", endaddr & mask);
269 }
270 if (va->va_addr2 != VRIPIFCF_ADDR2_DEFAULT)
271 aprint_normal(", 0x%08lx", va->va_addr2);
272 if (va->va_size2 != VRIPIFCF_SIZE2_DEFAULT)
273 aprint_normal("-%04lx",
274 (va->va_addr2 + va->va_size2 - 1) & 0xffff);
275
276 return (UNCONF);
277 }
278
279 int
vrip_search(device_t parent,cfdata_t cf,const int * ldesc,void * aux)280 vrip_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
281 {
282 struct vrip_softc *sc = device_private(parent);
283 struct vrip_attach_args va;
284 platid_mask_t mask;
285
286 if (cf->cf_loc[VRIPIFCF_PLATFORM] != VRIPIFCF_PLATFORM_DEFAULT) {
287 mask = PLATID_DEREF(cf->cf_loc[VRIPIFCF_PLATFORM]);
288 if (platid_match(&platid, &mask) == 0)
289 return (0);
290 }
291
292 memset(&va, 0, sizeof(va));
293 va.va_vc = &sc->sc_chipset;
294 va.va_iot = sc->sc_iot;
295 va.va_unit = cf->cf_loc[VRIPIFCF_UNIT];
296 va.va_addr = cf->cf_loc[VRIPIFCF_ADDR];
297 va.va_size = cf->cf_loc[VRIPIFCF_SIZE];
298 va.va_addr2 = cf->cf_loc[VRIPIFCF_ADDR2];
299 va.va_size2 = cf->cf_loc[VRIPIFCF_SIZE2];
300 va.va_gpio_chips = sc->sc_gpio_chips;
301 va.va_cc = sc->sc_chipset.vc_cc;
302 va.va_ac = sc->sc_chipset.vc_ac;
303 va.va_dc = sc->sc_chipset.vc_dc;
304 if (/*XXX*/config_probe(parent, cf, &va) == sc->sc_pri)
305 config_attach(parent, cf, &va, vrip_print, CFARGS_NONE);
306
307 return (0);
308 }
309
310 int
__vrip_power(vrip_chipset_tag_t vc,int unit,int onoff)311 __vrip_power(vrip_chipset_tag_t vc, int unit, int onoff)
312 {
313 struct vrip_softc *sc = vc->vc_sc;
314 const struct vrip_unit *vu;
315
316 if (sc->sc_chipset.vc_cc == NULL)
317 return (0); /* You have no clock mask unit yet. */
318 if (!VALID_UNIT(sc, unit))
319 return (0);
320 vu = &sc->sc_units[unit];
321
322 return (*sc->sc_chipset.vc_cc->cc_clock)(sc->sc_chipset.vc_cc,
323 vu->vu_clkmask, onoff);
324 }
325
326 vrip_intr_handle_t
__vrip_intr_establish(vrip_chipset_tag_t vc,int unit,int line,int level,int (* ih_fun)(void *),void * ih_arg)327 __vrip_intr_establish(vrip_chipset_tag_t vc, int unit, int line, int level,
328 int (*ih_fun)(void *), void *ih_arg)
329 {
330 struct vrip_softc *sc = vc->vc_sc;
331 const struct vrip_unit *vu;
332 struct intrhand *ih;
333
334 if (!VALID_UNIT(sc, unit))
335 return (NULL);
336 vu = &sc->sc_units[unit];
337 ih = &sc->sc_intrhands[vu->vu_intr[line]];
338 if (ih->ih_fun) /* Can't share level 1 interrupt */
339 return (NULL);
340 ih->ih_fun = ih_fun;
341 ih->ih_arg = ih_arg;
342 ih->ih_unit = vu;
343
344 /* Mask level 2 interrupt mask register. (disable interrupt) */
345 vrip_intr_setmask2(vc, ih, ~0, 0);
346 /* Unmask Level 1 interrupt mask register (enable interrupt) */
347 vrip_intr_setmask1(vc, ih, 1);
348
349 return ((void *)ih);
350 }
351
352 void
__vrip_intr_disestablish(vrip_chipset_tag_t vc,vrip_intr_handle_t handle)353 __vrip_intr_disestablish(vrip_chipset_tag_t vc, vrip_intr_handle_t handle)
354 {
355 struct intrhand *ih = handle;
356
357 ih->ih_fun = NULL;
358 ih->ih_arg = NULL;
359 /* Mask level 2 interrupt mask register(if any). (disable interrupt) */
360 vrip_intr_setmask2(vc, ih, ~0, 0);
361 /* Mask Level 1 interrupt mask register (disable interrupt) */
362 vrip_intr_setmask1(vc, ih, 0);
363 }
364
365 void
vrip_intr_suspend(void)366 vrip_intr_suspend(void)
367 {
368 struct vrip_softc *sc = the_vrip_sc;
369 bus_space_tag_t iot = sc->sc_iot;
370 bus_space_handle_t ioh = sc->sc_ioh;
371
372 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, (1<<VRIP_INTR_POWER));
373 bus_space_write_2 (iot, ioh, sc->sc_msysint2, 0);
374 }
375
376 void
vrip_intr_resume(void)377 vrip_intr_resume(void)
378 {
379 struct vrip_softc *sc = the_vrip_sc;
380 u_int32_t reg = sc->sc_intrmask;
381 bus_space_tag_t iot = sc->sc_iot;
382 bus_space_handle_t ioh = sc->sc_ioh;
383
384 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff);
385 bus_space_write_2 (iot, ioh, sc->sc_msysint2, (reg >> 16) & 0xffff);
386 }
387
388 /* Set level 1 interrupt mask. */
389 void
__vrip_intr_setmask1(vrip_chipset_tag_t vc,vrip_intr_handle_t handle,int enable)390 __vrip_intr_setmask1(vrip_chipset_tag_t vc, vrip_intr_handle_t handle,
391 int enable)
392 {
393 struct vrip_softc *sc = vc->vc_sc;
394 struct intrhand *ih = handle;
395 int level1 = ih - sc->sc_intrhands;
396 bus_space_tag_t iot = sc->sc_iot;
397 bus_space_handle_t ioh = sc->sc_ioh;
398 u_int32_t reg = sc->sc_intrmask;
399
400 DPRINTF(("__vrip_intr_setmask1: SYSINT: %s %d\n",
401 enable ? "enable" : "disable", level1));
402 reg = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) |
403 ((bus_space_read_2 (iot, ioh, sc->sc_msysint2) << 16)&0xffff0000);
404 if (enable)
405 reg |= (1 << level1);
406 else {
407 reg &= ~(1 << level1);
408 }
409 sc->sc_intrmask = reg;
410 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff);
411 bus_space_write_2 (iot, ioh, sc->sc_msysint2, (reg >> 16) & 0xffff);
412 DBG_BIT_PRINT(reg);
413
414 return;
415 }
416
417 void
__vrip_dump_level2mask(vrip_chipset_tag_t vc,vrip_intr_handle_t handle)418 __vrip_dump_level2mask(vrip_chipset_tag_t vc, vrip_intr_handle_t handle)
419 {
420 struct vrip_softc *sc = vc->vc_sc;
421 struct intrhand *ih = handle;
422 const struct vrip_unit *vu = ih->ih_unit;
423 u_int32_t reg;
424
425 if (vu->vu_mlreg) {
426 DPRINTF(("level1[%d] level2 mask:", vu->vu_intr[0]));
427 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg);
428 if (vu->vu_mhreg) { /* GIU [16:31] case only */
429 reg |= (bus_space_read_2(sc->sc_iot, sc->sc_ioh,
430 vu->vu_mhreg) << 16);
431 dbg_bit_print(reg);
432 } else
433 dbg_bit_print(reg);
434 }
435 }
436
437 /* Get level 2 interrupt status */
438 void
__vrip_intr_getstatus2(vrip_chipset_tag_t vc,vrip_intr_handle_t handle,u_int32_t * mask)439 __vrip_intr_getstatus2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle,
440 u_int32_t *mask /* Level 2 mask */)
441 {
442 struct vrip_softc *sc = vc->vc_sc;
443 struct intrhand *ih = handle;
444 const struct vrip_unit *vu = ih->ih_unit;
445 u_int32_t reg;
446
447 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh,
448 vu->vu_lreg);
449 reg |= ((bus_space_read_2(sc->sc_iot, sc->sc_ioh,
450 vu->vu_hreg) << 16)&0xffff0000);
451 /* dbg_bit_print(reg);*/
452 *mask = reg;
453 }
454
455 /* Set level 2 interrupt mask. */
456 void
__vrip_intr_setmask2(vrip_chipset_tag_t vc,vrip_intr_handle_t handle,u_int32_t mask,int onoff)457 __vrip_intr_setmask2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle,
458 u_int32_t mask /* Level 2 mask */, int onoff)
459 {
460 struct vrip_softc *sc = vc->vc_sc;
461 struct intrhand *ih = handle;
462 const struct vrip_unit *vu = ih->ih_unit;
463 u_int16_t reg;
464
465 DPRINTF(("vrip_intr_setmask2:\n"));
466 DUMP_LEVEL2MASK(vc, handle);
467 #ifdef WINCE_DEFAULT_SETTING
468 #warning WINCE_DEFAULT_SETTING
469 #else
470 if (vu->vu_mlreg) {
471 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg);
472 if (onoff)
473 reg |= (mask&0xffff);
474 else
475 reg &= ~(mask&0xffff);
476 bus_space_write_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg, reg);
477 if (vu->vu_mhreg != 0) { /* GIU [16:31] case only */
478 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh,
479 vu->vu_mhreg);
480 if (onoff)
481 reg |= ((mask >> 16) & 0xffff);
482 else
483 reg &= ~((mask >> 16) & 0xffff);
484 bus_space_write_2(sc->sc_iot, sc->sc_ioh,
485 vu->vu_mhreg, reg);
486 }
487 }
488 #endif /* WINCE_DEFAULT_SETTING */
489 DUMP_LEVEL2MASK(vc, handle);
490
491 return;
492 }
493
494 int
vrip_intr(void * arg,vaddr_t pc,u_int32_t status)495 vrip_intr(void *arg, vaddr_t pc, u_int32_t status)
496 {
497 struct vrip_softc *sc = (struct vrip_softc *)arg;
498 bus_space_tag_t iot = sc->sc_iot;
499 bus_space_handle_t ioh = sc->sc_ioh;
500 int i;
501 u_int32_t reg, mask;
502 /*
503 * Read level1 interrupt status.
504 */
505 reg = (bus_space_read_2 (iot, ioh, SYSINT1_REG_W)&0xffff) |
506 ((bus_space_read_2 (iot, ioh, sc->sc_sysint2)<< 16)&0xffff0000);
507 mask = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) |
508 ((bus_space_read_2 (iot, ioh, sc->sc_msysint2)<< 16)&0xffff0000);
509 reg &= mask;
510
511 /*
512 * Dispatch each handler.
513 */
514 for (i = 0; i < 32; i++) {
515 register struct intrhand *ih = &sc->sc_intrhands[i];
516 if (ih->ih_fun && (reg & (1 << i))) {
517 ih->ih_fun(ih->ih_arg);
518 }
519 }
520
521 return (1);
522 }
523
524 void
__vrip_register_cmu(vrip_chipset_tag_t vc,vrcmu_chipset_tag_t cmu)525 __vrip_register_cmu(vrip_chipset_tag_t vc, vrcmu_chipset_tag_t cmu)
526 {
527 struct vrip_softc *sc = vc->vc_sc;
528
529 sc->sc_chipset.vc_cc = cmu;
530 }
531
532 void
__vrip_register_gpio(vrip_chipset_tag_t vc,hpcio_chip_t chip)533 __vrip_register_gpio(vrip_chipset_tag_t vc, hpcio_chip_t chip)
534 {
535 struct vrip_softc *sc = vc->vc_sc;
536
537 if (chip->hc_chipid < 0 || VRIP_NIOCHIPS <= chip->hc_chipid)
538 panic("%s: '%s' has unknown id, %d", __func__,
539 chip->hc_name, chip->hc_chipid);
540 sc->sc_gpio_chips[chip->hc_chipid] = chip;
541 }
542
543 void
__vrip_register_dmaau(vrip_chipset_tag_t vc,vrdmaau_chipset_tag_t dmaau)544 __vrip_register_dmaau(vrip_chipset_tag_t vc, vrdmaau_chipset_tag_t dmaau)
545 {
546 struct vrip_softc *sc = vc->vc_sc;
547
548 sc->sc_chipset.vc_ac = dmaau;
549 }
550
551 void
__vrip_register_dcu(vrip_chipset_tag_t vc,vrdcu_chipset_tag_t dcu)552 __vrip_register_dcu(vrip_chipset_tag_t vc, vrdcu_chipset_tag_t dcu)
553 {
554 struct vrip_softc *sc = vc->vc_sc;
555
556 sc->sc_chipset.vc_dc = dcu;
557 }
558