1 /* $OpenBSD: rtl80x9reg.h,v 1.2 2003/10/21 18:58:49 jmc Exp $ */ 2 /* $NetBSD: rtl80x9reg.h,v 1.2 1998/10/31 00:31:43 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 /* 42 * Registers on RealTek 8019 and 8029 NE2000-compatible network interfaces. 43 * 44 * Data sheets for these chips can be found at: 45 * 46 * http://www.realtek.com.tw 47 */ 48 49 #ifndef _DEV_IC_RTL80x9_REG_H_ 50 #define _DEV_IC_RTL80x9_REG_H_ 51 52 /* 53 * Page 0 register offsets. 54 */ 55 #define NERTL_RTL0_8019ID0 0x0a /* 8019 ID Register 0 */ 56 #define RTL0_8019ID0 'P' 57 58 #define NERTL_RTL0_8019ID1 0x0b /* 8019 ID Register 1 */ 59 #define RTL0_8019ID1 'p' 60 61 /* 62 * Page 3 register offsets. 63 */ 64 #define NERTL_RTL3_EECR 0x01 /* EEPROM Command Register */ 65 #define RTL3_EECR_EEM1 0x80 /* EEPROM Operating Mode */ 66 #define RTL3_EECR_EEM0 0x40 67 /* 0 0 Normal operation */ 68 /* 0 1 Auto-load */ 69 /* 1 0 9346 programming */ 70 /* 1 1 Config register write enab */ 71 #define RTL3_EECR_EECS 0x08 /* EEPROM Chip Select */ 72 #define RTL3_EECR_EESK 0x04 /* EEPROM Clock */ 73 #define RTL3_EECR_EEDI 0x02 /* EEPROM Data In */ 74 #define RTL3_EECR_EEDO 0x01 /* EEPROM Data Out */ 75 76 #define NERTL_RTL3_BPAGE 0x02 /* BROM Page Register (8019) */ 77 78 #define NERTL_RTL3_CONFIG0 0x03 /* Configuration 0 (ro) */ 79 #define RTL3_CONFIG0_JP 0x08 /* jumper mode (8019) */ 80 #define RTL3_CONFIG0_BNC 0x04 /* BNC is active */ 81 82 #define NERTL_RTL3_CONFIG1 0x04 /* Configuration 1 (8019) */ 83 #define RTL3_CONFIG1_IRQEN 0x80 /* IRQ Enable */ 84 #define RTL3_CONFIG1_IRQS2 0x40 /* IRQ Select */ 85 #define RTL3_CONFIG1_IRQS1 0x20 86 #define RTL3_CONFIG1_IRQS0 0x10 87 /* 0 0 0 int 0 irq 2/9 */ 88 /* 0 0 1 int 1 irq 3 */ 89 /* 0 1 0 int 2 irq 4 */ 90 /* 0 1 1 int 3 irq 5 */ 91 /* 1 0 0 int 4 irq 10 */ 92 /* 1 0 1 int 5 irq 11 */ 93 /* 1 1 0 int 6 irq 12 */ 94 /* 1 1 1 int 7 irq 15 */ 95 #define RTL_CONFIG1_IOS3 0x08 /* I/O base Select */ 96 #define RTL_CONFIG1_IOS2 0x04 97 #define RTL_CONFIG1_IOS1 0x02 98 #define RTL_CONFIG1_IOS0 0x01 99 /* 0 0 0 0 0x300 */ 100 /* 0 0 0 1 0x320 */ 101 /* 0 0 1 0 0x340 */ 102 /* 0 0 1 1 0x360 */ 103 /* 0 1 0 0 0x380 */ 104 /* 0 1 0 1 0x3a0 */ 105 /* 0 1 1 0 0x3c0 */ 106 /* 0 1 1 1 0x3e0 */ 107 /* 1 0 0 0 0x200 */ 108 /* 1 0 0 1 0x220 */ 109 /* 1 0 1 0 0x240 */ 110 /* 1 0 1 1 0x260 */ 111 /* 1 1 0 0 0x280 */ 112 /* 1 1 0 1 0x2a0 */ 113 /* 1 1 1 0 0x2c0 */ 114 /* 1 1 1 1 0x2e0 */ 115 116 #define NERTL_RTL3_CONFIG2 0x05 /* Configuration 2 */ 117 #define RTL3_CONFIG2_PL1 0x80 /* Network media type */ 118 #define RTL3_CONFIG2_PL0 0x40 119 /* 0 0 TP/CX auto-detect */ 120 /* 0 1 10baseT */ 121 /* 1 0 10base5 */ 122 /* 1 1 10base2 */ 123 #define RTL3_CONFIG2_8029FCE 0x20 /* Flow Control Enable */ 124 #define RTL3_CONFIG2_8029PF 0x10 /* Pause Flag */ 125 #define RTL3_CONFIG2_8029BS1 0x02 /* Boot Rom Size */ 126 #define RTL3_CONFIG2_8029BS0 0x01 127 /* 0 0 No Boot Rom */ 128 /* 0 1 8k */ 129 /* 1 0 16k */ 130 /* 1 1 32k */ 131 #define RTL3_CONFIG2_8019BSELB 0x20 /* BROM disable */ 132 #define RTL3_CONFIG2_8019BS4 0x10 /* BROM size/base */ 133 #define RTL3_CONFIG2_8019BS3 0x08 134 #define RTL3_CONFIG2_8019BS2 0x04 135 #define RTL3_CONFIG2_8019BS1 0x02 136 #define RTL3_CONFIG2_8019BS0 0x01 137 138 #define NERTL_RTL3_CONFIG3 0x06 /* Configuration 3 */ 139 #define RTL3_CONFIG3_8019PNP 0x80 /* PnP Mode */ 140 #define RTL3_CONFIG3_FUDUP 0x40 /* Full Duplex */ 141 #define RTL3_CONFIG3_LEDS1 0x20 /* LED1/2 pin configuration */ 142 /* 0 LED1 == LED_RX, LED2 == LED_TX */ 143 /* 1 LED1 == LED_CRS, LED2 == MCSB */ 144 #define RTL3_CONFIG3_LEDS0 0x10 /* LED0 pin configuration */ 145 /* 0 LED0 pin == LED_COL */ 146 /* 1 LED0 pin == LED_LINK */ 147 #define RTL3_CONFIG3_SLEEP 0x04 /* Sleep mode */ 148 #define RTL3_CONFIG3_PWRDN 0x02 /* Power Down */ 149 #define RTL3_CONFIG3_8019ACTIVEB 0x01 /* inverse of bit 0 in PnP Act Reg */ 150 151 #define NERTL_RTL3_CSNSAV 0x08 /* CSN Save Register (8019) */ 152 153 #define NERTL_RTL3_HLTCLK 0x09 /* Halt Clock */ 154 #define RTL3_HLTCLK_RUNNING 'R' /* clock runs in power down */ 155 #define RTL3_HLTCLK_HALTED 'H' /* clock halted in power down */ 156 157 #define NERTL_RTL3_INTR 0x0b /* ISA bus states of INT7-0 (8019) */ 158 159 #define NERTL_RTL3_8029ID0 0x0e /* ID register 0 */ 160 161 #define NERTL_RTL3_8029ID1 0x0f /* ID register 1 */ 162 163 #endif /* _DEV_IC_RTL80x9_REG_H_ */ 164