1 /* $OpenBSD: ctlreg.h,v 1.7 2003/06/02 23:27:54 millert Exp $ */ 2 /* $NetBSD: ctlreg.h,v 1.15 1997/07/20 18:55:03 pk Exp $ */ 3 4 /* 5 * Copyright (c) 1996 6 * The President and Fellows of Harvard College. All rights reserved. 7 * Copyright (c) 1992, 1993 8 * The Regents of the University of California. All rights reserved. 9 * 10 * This software was developed by the Computer Systems Engineering group 11 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 12 * contributed to Berkeley. 13 * 14 * All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Harvard University. 17 * This product includes software developed by the University of 18 * California, Lawrence Berkeley Laboratory. 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 1. Redistributions of source code must retain the above copyright 24 * notice, this list of conditions and the following disclaimer. 25 * 2. Redistributions in binary form must reproduce the above copyright 26 * notice, this list of conditions and the following disclaimer in the 27 * documentation and/or other materials provided with the distribution. 28 * 3. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)ctlreg.h 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * Sun4m support by Aaron Brown, Harvard University. 49 * Changes Copyright (c) 1995 The President and Fellows of Harvard College. 50 * All rights reserved. 51 */ 52 53 /* 54 * Sun 4, 4c, and 4m control registers. (includes address space definitions 55 * and some registers in control space). 56 */ 57 58 /* 59 * The Alternate address spaces. 60 */ 61 62 /* 0x00 unused */ 63 /* 0x01 unused */ 64 #define ASI_CONTROL 0x02 /* cache enable, context reg, etc */ 65 #define ASI_SEGMAP 0x03 /* [4/4c] segment maps */ 66 #define ASI_SRMMUFP 0x03 /* [4m] ref mmu flush/probe */ 67 #define ASI_PTE 0x04 /* [4/4c] PTE space (pmegs) */ 68 #define ASI_SRMMU 0x04 /* [4m] ref mmu registers */ 69 #define ASI_REGMAP 0x06 /* [4/3-level MMU ] region maps */ 70 #define ASI_HWFLUSHSEG 0x05 /* [4/4c] hardware assisted version of FLUSHSEG */ 71 #define ASI_HWFLUSHPG 0x06 /* [4/4c] hardware assisted version of FLUSHPG */ 72 #define ASI_SRMMUDIAG 0x06 /* [4m] */ 73 #define ASI_HWFLUSHCTX 0x07 /* [4/4c] hardware assisted version of FLUSHCTX */ 74 75 #define ASI_USERI 0x08 /* I-space (user) */ 76 #define ASI_KERNELI 0x09 /* I-space (kernel) */ 77 #define ASI_USERD 0x0a /* D-space (user) */ 78 #define ASI_KERNELD 0x0b /* D-space (kernel) */ 79 80 #define ASI_FLUSHREG 0x7 /* [4/4c] flush cache by region */ 81 #define ASI_FLUSHSEG 0x0c /* [4/4c] flush cache by segment */ 82 #define ASI_FLUSHPG 0x0d /* [4/4c] flush cache by page */ 83 #define ASI_FLUSHCTX 0x0e /* [4/4c] flush cache by context */ 84 85 #define ASI_DCACHE 0x0f /* [4] flush data cache */ 86 87 #define ASI_ICACHETAG 0x0c /* [4m] instruction cache tag */ 88 #define ASI_ICACHEDATA 0x0d /* [4m] instruction cache data */ 89 #define ASI_DCACHETAG 0x0e /* [4m] data cache tag */ 90 #define ASI_DCACHEDATA 0x0f /* [4m] data cache data */ 91 #define ASI_IDCACHELFP 0x10 /* [4m] flush i&d cache line (page) */ 92 #define ASI_IDCACHELFS 0x11 /* [4m] flush i&d cache line (seg) */ 93 #define ASI_IDCACHELFR 0x12 /* [4m] flush i&d cache line (reg) */ 94 #define ASI_IDCACHELFC 0x13 /* [4m] flush i&d cache line (ctxt) */ 95 #define ASI_IDCACHELFU 0x14 /* [4m] flush i&d cache line (user) */ 96 #define ASI_BYPASS 0x20 /* [4m] sun ref mmu bypass, 97 ie. direct phys access */ 98 #define ASI_HICACHECLR 0x31 /* [4m] hypersparc only: I-cache flash clear */ 99 #define ASI_ICACHECLR 0x36 /* [4m] ms1 only: I-cache flash clear */ 100 #define ASI_DCACHECLR 0x37 /* [4m] ms1 only: D-cache flash clear */ 101 #define ASI_DCACHEDIAG 0x39 /* [4m] data cache diagnostic register access */ 102 103 /* 104 * [4/4c] Registers in the control space (ASI_CONTROL). 105 */ 106 #define AC_IDPROM 0x00000000 /* [4] ID PROM */ 107 #define AC_CONTEXT 0x30000000 /* [4/4c] context register (byte) */ 108 #define AC_SYSENABLE 0x40000000 /* [4/4c] system enable register (byte) */ 109 #define AC_DVMA_ENABLE 0x50000000 /* [4] enable user dvma */ 110 #define AC_BUS_ERR 0x60000000 /* [4] bus error register */ 111 #define AC_SYNC_ERR 0x60000000 /* [4c] sync (memory) error reg */ 112 #define AC_SYNC_VA 0x60000004 /* [4c] sync error virtual addr */ 113 #define AC_ASYNC_ERR 0x60000008 /* [4c] async error reg */ 114 #define AC_ASYNC_VA 0x6000000c /* [4c] async error virtual addr */ 115 #define AC_DIAG_REG 0x70000000 /* [4] diagnostic reg */ 116 #define AC_CACHETAGS 0x80000000 /* [4/4c?] cache tag base address */ 117 #define AC_CACHEDATA 0x90000000 /* [4] cached data [sun4/400?] */ 118 #define AC_DVMA_MAP 0xd0000000 /* [4] user dvma map entries */ 119 #define AC_VMEINTVEC 0xe0000000 /* [4] vme interrupt vector */ 120 #define AC_SERIAL 0xf0000000 /* [4/4c] special serial port sneakiness */ 121 /* AC_SERIAL is not used in the kernel (it is for the PROM) */ 122 123 /* XXX: does not belong here */ 124 #define ME_REG_IERR 0x80 /* memory err ctrl reg error intr pending bit */ 125 126 /* 127 * [4/4c] 128 * Bits in sync error register. Reading the register clears these; 129 * otherwise they accumulate. The error(s) occurred at the virtual 130 * address stored in the sync error address register, and may have 131 * been due to, e.g., what would usually be called a page fault. 132 * Worse, the bits accumulate during instruction prefetch, so 133 * various bits can be on that should be off. 134 */ 135 #define SER_WRITE 0x8000 /* error occurred during write */ 136 #define SER_INVAL 0x80 /* PTE had PG_V off */ 137 #define SER_PROT 0x40 /* operation violated PTE prot */ 138 #define SER_TIMEOUT 0x20 /* bus timeout (non-existent mem) */ 139 #define SER_SBUSERR 0x10 /* S-Bus bus error */ 140 #define SER_MEMERR 0x08 /* memory ecc/parity error */ 141 #define SER_SZERR 0x02 /* [4/vme?] size error, whatever that is */ 142 #define SER_WATCHDOG 0x01 /* watchdog reset (never see this) */ 143 144 #define SER_BITS \ 145 "\20\20WRITE\10INVAL\7PROT\6TIMEOUT\5SBUSERR\4MEMERR\2SZERR\1WATCHDOG" 146 147 /* 148 * [4/4c] 149 * Bits in async error register (errors from DVMA or Sun-4 cache 150 * writeback). The corresponding bit is also set in the sync error reg. 151 * 152 * A writeback invalid error means there is a bug in the PTE manager. 153 * 154 * The word is that the async error register does not work right. 155 */ 156 #define AER_WBINVAL 0x80 /* writeback found PTE without PG_V */ 157 #define AER_TIMEOUT 0x20 /* bus timeout */ 158 #define AER_DVMAERR 0x10 /* bus error during DVMA */ 159 160 #define AER_BITS "\20\10WBINVAL\6TIMEOUT\5DVMAERR" 161 162 /* 163 * [4/4c] Bits in system enable register. 164 */ 165 #define SYSEN_DVMA 0x20 /* Enable dvma */ 166 #define SYSEN_CACHE 0x10 /* Enable cache */ 167 #define SYSEN_IOCACHE 0x40 /* Enable IO cache */ 168 #define SYSEN_VIDEO 0x08 /* Enable on-board video */ 169 #define SYSEN_RESET 0x04 /* Reset the hardware */ 170 #define SYSEN_RESETVME 0x02 /* Reset the VME bus */ 171 172 173 /* 174 * [4m] Bits in ASI_CONTROL? space, sun4m only. 175 */ 176 #define MXCC_ENABLE_ADDR 0x1c00a00 /* Enable register for MXCC */ 177 #define MXCC_ENABLE_BIT 0x4 /* Enable bit for MXCC */ 178 179 /* 180 * Bits in ASI_SRMMUFP space. 181 * Bits 8-11 determine the type of flush/probe. 182 * Address bits 12-31 hold the page frame. 183 */ 184 #define ASI_SRMMUFP_L3 (0<<8) /* probe L3 | flush L3 PTE */ 185 #define ASI_SRMMUFP_L2 (1<<8) /* probe L2 | flush L2/L3 PTE/PTD's */ 186 #define ASI_SRMMUFP_L1 (2<<8) /* probe L1 | flush L1/L2/L3 PTE/PTD's*/ 187 #define ASI_SRMMUFP_L0 (3<<8) /* probe L0 | flush L0/L1/L2/L3 PTE/PTD's */ 188 #define ASI_SRMMUFP_LN (4<<8) /* probe all | flush all levels */ 189 190 /* 191 * [4m] Registers and bits in the SPARC Reference MMU (ASI_SRMMU). 192 */ 193 #define SRMMU_PCR 0x00000000 /* Processor control register */ 194 #define SRMMU_CXTPTR 0x00000100 /* Context table pointer register */ 195 #define SRMMU_CXR 0x00000200 /* Context register */ 196 #define SRMMU_SFSR 0x00000300 /* Synchronous fault status reg */ 197 #define SRMMU_SFAR 0x00000400 /* Synchronous fault address reg */ 198 #define SRMMU_AFSR 0x00000500 /* Asynchronous fault status reg (HS)*/ 199 #define SRMMU_AFAR 0x00000600 /* Asynchronous fault address reg (HS)*/ 200 #define SRMMU_PCFG 0x00000600 /* Processor configuration reg (TURBO)*/ 201 #define SRMMU_TLBCTRL 0x00001000 /* TLB replacement control reg */ 202 203 204 /* 205 * [4m] Bits in SRMMU control register. One set per module. 206 */ 207 #define VIKING_PCR_ME 0x00000001 /* MMU Enable */ 208 #define VIKING_PCR_NF 0x00000002 /* Fault inhibit bit */ 209 #define VIKING_PCR_PSO 0x00000080 /* Partial Store Ordering enable */ 210 #define VIKING_PCR_DCE 0x00000100 /* Data cache enable bit */ 211 #define VIKING_PCR_ICE 0x00000200 /* SuperSPARC instr. cache enable */ 212 #define VIKING_PCR_SB 0x00000400 /* Store buffer enable bit */ 213 #define VIKING_PCR_MB 0x00000800 /* MBus mode: 0=MXCC, 1=no MXCC */ 214 #define VIKING_PCR_PE 0x00001000 /* Enable memory parity checking */ 215 #define VIKING_PCR_BM 0x00002000 /* 1 iff booting */ 216 #define VIKING_PCR_SE 0x00004000 /* Coherent bus snoop enable */ 217 #define VIKING_PCR_AC 0x00008000 /* 1=cache non-MMU accesses */ 218 #define VIKING_PCR_TC 0x00010000 /* 1=cache table walks */ 219 220 #define HYPERSPARC_PCR_ME 0x00000001 /* MMU Enable */ 221 #define HYPERSPARC_PCR_NF 0x00000002 /* Fault inhibit bit */ 222 #define HYPERSPARC_PCR_CE 0x00000100 /* Cache enable bit */ 223 #define HYPERSPARC_PCR_CM 0x00000400 /* Cache mode: 1=write-back */ 224 #define HYPERSPARC_PCR_MR 0x00000800 /* Memory reflection: 1 = on */ 225 #define HYPERSPARC_PCR_CS 0x00001000 /* cache size: 1=256k, 0=128k */ 226 #define HYPERSPARC_PCR_C 0x00002000 /* enable cache when MMU off */ 227 #define HYPERSPARC_PCR_BM 0x00004000 /* 1 iff booting */ 228 #define HYPERSPARC_PCR_MID 0x00078000 /* MBus module ID MID<3:0> */ 229 #define HYPERSPARC_PCR_WBE 0x00080000 /* Write buffer enable */ 230 #define HYPERSPARC_PCR_SE 0x00100000 /* Coherent bus snoop enable */ 231 #define HYPERSPARC_PCR_CWR 0x00200000 /* Cache wrap enable */ 232 233 #define CYPRESS_PCR_ME 0x00000001 /* MMU Enable */ 234 #define CYPRESS_PCR_NF 0x00000002 /* Fault inhibit bit */ 235 #define CYPRESS_PCR_CE 0x00000100 /* Cache enable bit */ 236 #define CYPRESS_PCR_CL 0x00000200 /* Cache Lock (604 only) */ 237 #define CYPRESS_PCR_CM 0x00000400 /* Cache mode: 1=write-back */ 238 #define CYPRESS_PCR_MR 0x00000800 /* Memory reflection: 1=on (605 only) */ 239 #define CYPRESS_PCR_C 0x00002000 /* enable cache when MMU off */ 240 #define CYPRESS_PCR_BM 0x00004000 /* 1 iff booting */ 241 #define CYPRESS_PCR_MID 0x00078000 /* MBus module ID MID<3:0> (605 only) */ 242 #define CYPRESS_PCR_MV 0x00080000 /* Multichip Valid */ 243 #define CYPRESS_PCR_MCM 0x00300000 /* Multichip Mask */ 244 #define CYPRESS_PCR_MCA 0x00c00000 /* Multichip Address */ 245 246 #define MS1_PCR_ME 0x00000001 /* MMU Enable */ 247 #define MS1_PCR_NF 0x00000002 /* Fault inhibit bit */ 248 #define MS1_PCR_DCE 0x00000100 /* Data cache enable */ 249 #define MS1_PCR_ICE 0x00000200 /* Instruction cache enable */ 250 #define MS1_PCR_RC 0x00000c00 /* DRAM Refresh control */ 251 #define MS1_PCR_PE 0x00001000 /* Enable memory parity checking */ 252 #define MS1_PCR_BM 0x00004000 /* 1 iff booting */ 253 #define MS1_PCR_AC 0x00008000 /* 1=cache if ME==0 (and [ID]CE on) */ 254 #define MS1_PCR_ID 0x00010000 /* 1=disable ITBR */ 255 #define MS1_PCR_PC 0x00020000 /* Parity control: 0=even,1=odd */ 256 #define MS1_PCR_MV 0x00100000 /* Memory data View (diag) */ 257 #define MS1_PCR_DV 0x00200000 /* Data View (diag) */ 258 #define MS1_PCR_AV 0x00400000 /* Address View (diag) */ 259 #define MS1_PCR_STW 0x00800000 /* Software Tablewalk enable */ 260 261 #define SWIFT_PCR_ME 0x00000001 /* MMU Enable */ 262 #define SWIFT_PCR_NF 0x00000002 /* Fault inhibit bit */ 263 #define SWIFT_PCR_DCE 0x00000100 /* Data cache enable */ 264 #define SWIFT_PCR_ICE 0x00000200 /* Instruction cache enable */ 265 #define SWIFT_PCR_RC 0x00003c00 /* DRAM Refresh control */ 266 #define SWIFT_PCR_BM 0x00004000 /* 1 iff booting */ 267 #define SWIFT_PCR_AC 0x00008000 /* 1=cache if ME=0 (and [ID]CE on) */ 268 #define SWIFT_PCR_PA 0x00010000 /* TCX/SX control */ 269 #define SWIFT_PCR_PC 0x00020000 /* Parity control: 0=even,1=odd */ 270 #define SWIFT_PCR_PE 0x00040000 /* Enable memory parity checking */ 271 #define SWIFT_PCR_PMC 0x00180000 /* Page mode control */ 272 #define SWIFT_PCR_BF 0x00200000 /* Branch Folding */ 273 #define SWIFT_PCR_WP 0x00400000 /* Watch point enable */ 274 #define SWIFT_PCR_STW 0x00800000 /* Software Tablewalk enable */ 275 276 #define TURBOSPARC_PCR_ME 0x00000001 /* MMU Enable */ 277 #define TURBOSPARC_PCR_NF 0x00000002 /* Fault inhibit bit */ 278 #define TURBOSPARC_PCR_ICS 0x00000004 /* I-cache snoop enable */ 279 #define TURBOSPARC_PCR_PSO 0x00000008 /* Partial Store order (ro!) */ 280 #define TURBOSPARC_PCR_DCE 0x00000100 /* Data cache enable */ 281 #define TURBOSPARC_PCR_ICE 0x00000200 /* Instruction cache enable */ 282 #define TURBOSPARC_PCR_RC 0x00003c00 /* DRAM Refresh control */ 283 #define TURBOSPARC_PCR_BM 0x00004000 /* 1 iff booting */ 284 #define TURBOSPARC_PCR_PC 0x00020000 /* Parity ctrl: 0=even,1=odd */ 285 #define TURBOSPARC_PCR_PE 0x00040000 /* Enable parity checking */ 286 #define TURBOSPARC_PCR_PMC 0x00180000 /* Page mode control */ 287 288 /* The Turbosparc's Processor Configuration Register */ 289 #define TURBOSPARC_PCFG_SCC 0x00000007 /* e-cache config */ 290 #define TURBOSPARC_PCFG_SE 0x00000008 /* e-cache enable */ 291 #define TURBOSPARC_PCFG_US2 0x00000010 /* microsparc II compat */ 292 #define TURBOSPARC_PCFG_WT 0x00000020 /* write-through enable */ 293 #define TURBOSPARC_PCFG_SBC 0x000000c0 /* SBus Clock */ 294 #define TURBOSPARC_PCFG_WS 0x03800000 /* DRAM wait states */ 295 #define TURBOSPARC_PCFG_RAH 0x0c000000 /* DRAM Row Address Hold */ 296 #define TURBOSPARC_PCFG_AXC 0x30000000 /* AFX Clock */ 297 #define TURBOSPARC_PCFG_SNP 0x40000000 /* DVMA Snoop enable */ 298 #define TURBOSPARC_PCFG_IOCLK 0x80000000 /* I/O clock ratio */ 299 300 301 /* Implementation and Version fields are common to all modules */ 302 #define SRMMU_PCR_VER 0x0f000000 /* Version of MMU implementation */ 303 #define SRMMU_PCR_IMPL 0xf0000000 /* Implementation number of MMU */ 304 305 306 /* [4m] Bits in the Synchronous Fault Status Register */ 307 #define SFSR_EM 0x00020000 /* Error mode watchdog reset occurred */ 308 #define SFSR_CS 0x00010000 /* Control Space error */ 309 #define SFSR_PERR 0x00006000 /* Parity error code */ 310 #define SFSR_SB 0x00008000 /* SS: Store Buffer Error */ 311 #define SFSR_P 0x00004000 /* SS: Parity error */ 312 #define SFSR_UC 0x00001000 /* Uncorrectable error */ 313 #define SFSR_TO 0x00000800 /* S-Bus timeout */ 314 #define SFSR_BE 0x00000400 /* S-Bus bus error */ 315 #define SFSR_LVL 0x00000300 /* Pagetable level causing the fault */ 316 #define SFSR_AT 0x000000e0 /* Access type */ 317 #define SFSR_FT 0x0000001c /* Fault type */ 318 #define SFSR_FAV 0x00000002 /* Fault Address is valid */ 319 #define SFSR_OW 0x00000001 /* Overwritten with new fault */ 320 321 #define SFSR_BITS \ 322 "\20\21CSERR\17PARITY\16SYSERR\15UNCORR\14TIMEOUT\13BUSERR\2FAV\1OW" 323 324 /* [4m] Synchronous Fault Types */ 325 #define SFSR_FT_NONE (0 << 2) /* no fault */ 326 #define SFSR_FT_INVADDR (1 << 2) /* invalid address fault */ 327 #define SFSR_FT_PROTERR (2 << 2) /* protection fault */ 328 #define SFSR_FT_PRIVERR (3 << 2) /* privelege violation */ 329 #define SFSR_FT_TRANSERR (4 << 2) /* translation fault */ 330 #define SFSR_FT_BUSERR (5 << 2) /* access bus error */ 331 #define SFSR_FT_INTERR (6 << 2) /* internal error */ 332 #define SFSR_FT_RESERVED (7 << 2) /* reserved */ 333 334 /* [4m] Synchronous Fault Access Types */ 335 #define SFSR_AT_LDUDATA (0 << 5) /* Load user data */ 336 #define SFSR_AT_LDSDATA (1 << 5) /* Load supervisor data */ 337 #define SFSR_AT_LDUTEXT (2 << 5) /* Load user text */ 338 #define SFSR_AT_LDSTEXT (3 << 5) /* Load supervisor text */ 339 #define SFSR_AT_STUDATA (4 << 5) /* Store user data */ 340 #define SFSR_AT_STSDATA (5 << 5) /* Store supervisor data */ 341 #define SFSR_AT_STUTEXT (6 << 5) /* Store user text */ 342 #define SFSR_AT_STSTEXT (7 << 5) /* Store supervisor text */ 343 #define SFSR_AT_SUPERVISOR (1 << 5) /* Set iff supervisor */ 344 #define SFSR_AT_TEXT (2 << 5) /* Set iff text */ 345 #define SFSR_AT_STORE (4 << 5) /* Set iff store */ 346 347 /* [4m] Synchronous Fault PT Levels */ 348 #define SFSR_LVL_0 (0 << 8) /* Context table entry */ 349 #define SFSR_LVL_1 (1 << 8) /* Region table entry */ 350 #define SFSR_LVL_2 (2 << 8) /* Segment table entry */ 351 #define SFSR_LVL_3 (3 << 8) /* Page table entry */ 352 353 /* [4m] Asynchronous Fault Status Register bits */ 354 #define AFSR_AFO 0x00000001 /* Async. fault occurred */ 355 #define AFSR_AFA 0x000000f0 /* Bits <35:32> of faulting phys addr */ 356 #define AFSR_AFA_RSHIFT 4 /* Shift to get AFA to bit 0 */ 357 #define AFSR_AFA_LSHIFT 28 /* Shift to get AFA to bit 32 */ 358 #define AFSR_BE 0x00000400 /* Bus error */ 359 #define AFSR_TO 0x00000800 /* Bus timeout */ 360 #define AFSR_UC 0x00001000 /* Uncorrectable error */ 361 #define AFSR_SE 0x00002000 /* System error */ 362 363 #define AFSR_BITS "\20\16SYSERR\15UNCORR\14TIMEOUT\13BUSERR\1AFO" 364 365 /* [4m] TLB Replacement Control Register bits */ 366 #define TLBC_DISABLE 0x00000020 /* Disable replacement counter */ 367 #define TLBC_RCNTMASK 0x0000001f /* Replacement counter (0-31) */ 368 369 /* 370 * The Ross Hypersparc has an Instruction Cache Control Register (ICCR) 371 * It contains an enable bit for the on-chip instruction cache and a bit 372 * that controls whether a FLUSH instruction causes an Unimplemented 373 * Flush Trap or just flushes the appropriate instruction cache line. 374 * The ICCR register is implemented as Ancillary State register number 31. 375 */ 376 #define HYPERSPARC_ICCR_ICE 1 /* Instruction cache enable */ 377 #define HYPERSPARC_ICCR_FTD 2 /* Unimpl. flush trap disable */ 378 #define HYPERSPARC_ASRNUM_ICCR 31 /* ICCR == ASR#31 */ 379