1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD: stable/9/sys/dev/drm2/radeon/rs690.c 263170 2014-03-14 12:37:42Z dumbbell $");
31
32 #include <sys/limits.h>
33
34 #include <dev/drm2/drmP.h>
35 #include "radeon.h"
36 #include "radeon_asic.h"
37 #include "atom.h"
38 #include "rs690d.h"
39
rs690_mc_wait_for_idle(struct radeon_device * rdev)40 int rs690_mc_wait_for_idle(struct radeon_device *rdev)
41 {
42 unsigned i;
43 uint32_t tmp;
44
45 for (i = 0; i < rdev->usec_timeout; i++) {
46 /* read MC_STATUS */
47 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
48 if (G_000090_MC_SYSTEM_IDLE(tmp))
49 return 0;
50 DRM_UDELAY(1);
51 }
52 return -1;
53 }
54
rs690_gpu_init(struct radeon_device * rdev)55 static void rs690_gpu_init(struct radeon_device *rdev)
56 {
57 /* FIXME: is this correct ? */
58 r420_pipes_init(rdev);
59 if (rs690_mc_wait_for_idle(rdev)) {
60 DRM_ERROR("Failed to wait MC idle while "
61 "programming pipes. Bad things might happen.\n");
62 }
63 }
64
65 union igp_info {
66 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
67 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
68 };
69
rs690_pm_info(struct radeon_device * rdev)70 void rs690_pm_info(struct radeon_device *rdev)
71 {
72 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
73 union igp_info *info;
74 uint16_t data_offset;
75 uint8_t frev, crev;
76 fixed20_12 tmp;
77
78 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
79 &frev, &crev, &data_offset)) {
80 info = (union igp_info *)((uintptr_t)rdev->mode_info.atom_context->bios + data_offset);
81
82 /* Get various system informations from bios */
83 switch (crev) {
84 case 1:
85 tmp.full = dfixed_const(100);
86 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
87 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
88 if (le16_to_cpu(info->info.usK8MemoryClock))
89 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
90 else if (rdev->clock.default_mclk) {
91 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
92 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
93 } else
94 rdev->pm.igp_system_mclk.full = dfixed_const(400);
95 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
96 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
97 break;
98 case 2:
99 tmp.full = dfixed_const(100);
100 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
101 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
102 if (le32_to_cpu(info->info_v2.ulBootUpUMAClock))
103 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
104 else if (rdev->clock.default_mclk)
105 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
106 else
107 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
108 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
109 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
110 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
111 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
112 break;
113 default:
114 /* We assume the slower possible clock ie worst case */
115 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
116 rdev->pm.igp_system_mclk.full = dfixed_const(200);
117 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
118 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
119 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
120 break;
121 }
122 } else {
123 /* We assume the slower possible clock ie worst case */
124 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
125 rdev->pm.igp_system_mclk.full = dfixed_const(200);
126 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
127 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
128 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
129 }
130 /* Compute various bandwidth */
131 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
132 tmp.full = dfixed_const(4);
133 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
134 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
135 * = ht_clk * ht_width / 5
136 */
137 tmp.full = dfixed_const(5);
138 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
139 rdev->pm.igp_ht_link_width);
140 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
141 if (tmp.full < rdev->pm.max_bandwidth.full) {
142 /* HT link is a limiting factor */
143 rdev->pm.max_bandwidth.full = tmp.full;
144 }
145 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
146 * = (sideport_clk * 14) / 10
147 */
148 tmp.full = dfixed_const(14);
149 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
150 tmp.full = dfixed_const(10);
151 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
152 }
153
rs690_mc_init(struct radeon_device * rdev)154 static void rs690_mc_init(struct radeon_device *rdev)
155 {
156 u64 base;
157
158 rs400_gart_adjust_size(rdev);
159 rdev->mc.vram_is_ddr = true;
160 rdev->mc.vram_width = 128;
161 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
162 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
163 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
164 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
165 rdev->mc.visible_vram_size = rdev->mc.aper_size;
166 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
167 base = G_000100_MC_FB_START(base) << 16;
168 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
169 rs690_pm_info(rdev);
170 radeon_vram_location(rdev, &rdev->mc, base);
171 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
172 radeon_gtt_location(rdev, &rdev->mc);
173 radeon_update_bandwidth_info(rdev);
174 }
175
rs690_line_buffer_adjust(struct radeon_device * rdev,struct drm_display_mode * mode1,struct drm_display_mode * mode2)176 void rs690_line_buffer_adjust(struct radeon_device *rdev,
177 struct drm_display_mode *mode1,
178 struct drm_display_mode *mode2)
179 {
180 u32 tmp;
181
182 /*
183 * Line Buffer Setup
184 * There is a single line buffer shared by both display controllers.
185 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
186 * the display controllers. The paritioning can either be done
187 * manually or via one of four preset allocations specified in bits 1:0:
188 * 0 - line buffer is divided in half and shared between crtc
189 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
190 * 2 - D1 gets the whole buffer
191 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
192 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
193 * allocation mode. In manual allocation mode, D1 always starts at 0,
194 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
195 */
196 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
197 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
198 /* auto */
199 if (mode1 && mode2) {
200 if (mode1->hdisplay > mode2->hdisplay) {
201 if (mode1->hdisplay > 2560)
202 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
203 else
204 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
205 } else if (mode2->hdisplay > mode1->hdisplay) {
206 if (mode2->hdisplay > 2560)
207 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
208 else
209 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
210 } else
211 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
212 } else if (mode1) {
213 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
214 } else if (mode2) {
215 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
216 }
217 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
218 }
219
220 struct rs690_watermark {
221 u32 lb_request_fifo_depth;
222 fixed20_12 num_line_pair;
223 fixed20_12 estimated_width;
224 fixed20_12 worst_case_latency;
225 fixed20_12 consumption_rate;
226 fixed20_12 active_time;
227 fixed20_12 dbpp;
228 fixed20_12 priority_mark_max;
229 fixed20_12 priority_mark;
230 fixed20_12 sclk;
231 };
232
rs690_crtc_bandwidth_compute(struct radeon_device * rdev,struct radeon_crtc * crtc,struct rs690_watermark * wm)233 static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
234 struct radeon_crtc *crtc,
235 struct rs690_watermark *wm)
236 {
237 struct drm_display_mode *mode = &crtc->base.mode;
238 fixed20_12 a, b, c;
239 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
240 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
241
242 if (!crtc->base.enabled) {
243 /* FIXME: wouldn't it better to set priority mark to maximum */
244 wm->lb_request_fifo_depth = 4;
245 return;
246 }
247
248 if (crtc->vsc.full > dfixed_const(2))
249 wm->num_line_pair.full = dfixed_const(2);
250 else
251 wm->num_line_pair.full = dfixed_const(1);
252
253 b.full = dfixed_const(mode->crtc_hdisplay);
254 c.full = dfixed_const(256);
255 a.full = dfixed_div(b, c);
256 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
257 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
258 if (a.full < dfixed_const(4)) {
259 wm->lb_request_fifo_depth = 4;
260 } else {
261 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
262 }
263
264 /* Determine consumption rate
265 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
266 * vtaps = number of vertical taps,
267 * vsc = vertical scaling ratio, defined as source/destination
268 * hsc = horizontal scaling ration, defined as source/destination
269 */
270 a.full = dfixed_const(mode->clock);
271 b.full = dfixed_const(1000);
272 a.full = dfixed_div(a, b);
273 pclk.full = dfixed_div(b, a);
274 if (crtc->rmx_type != RMX_OFF) {
275 b.full = dfixed_const(2);
276 if (crtc->vsc.full > b.full)
277 b.full = crtc->vsc.full;
278 b.full = dfixed_mul(b, crtc->hsc);
279 c.full = dfixed_const(2);
280 b.full = dfixed_div(b, c);
281 consumption_time.full = dfixed_div(pclk, b);
282 } else {
283 consumption_time.full = pclk.full;
284 }
285 a.full = dfixed_const(1);
286 wm->consumption_rate.full = dfixed_div(a, consumption_time);
287
288
289 /* Determine line time
290 * LineTime = total time for one line of displayhtotal
291 * LineTime = total number of horizontal pixels
292 * pclk = pixel clock period(ns)
293 */
294 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
295 line_time.full = dfixed_mul(a, pclk);
296
297 /* Determine active time
298 * ActiveTime = time of active region of display within one line,
299 * hactive = total number of horizontal active pixels
300 * htotal = total number of horizontal pixels
301 */
302 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
303 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
304 wm->active_time.full = dfixed_mul(line_time, b);
305 wm->active_time.full = dfixed_div(wm->active_time, a);
306
307 /* Maximun bandwidth is the minimun bandwidth of all component */
308 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
309 if (rdev->mc.igp_sideport_enabled) {
310 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
311 rdev->pm.sideport_bandwidth.full)
312 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
313 #ifdef DUMBBELL_WIP
314 read_delay_latency.full = dfixed_const(370 * 800 * 1000);
315 #endif /* DUMBBELL_WIP */
316 read_delay_latency.full = UINT_MAX;
317 read_delay_latency.full = dfixed_div(read_delay_latency,
318 rdev->pm.igp_sideport_mclk);
319 } else {
320 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
321 rdev->pm.k8_bandwidth.full)
322 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
323 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
324 rdev->pm.ht_bandwidth.full)
325 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
326 read_delay_latency.full = dfixed_const(5000);
327 }
328
329 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
330 a.full = dfixed_const(16);
331 rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
332 a.full = dfixed_const(1000);
333 rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
334 /* Determine chunk time
335 * ChunkTime = the time it takes the DCP to send one chunk of data
336 * to the LB which consists of pipeline delay and inter chunk gap
337 * sclk = system clock(ns)
338 */
339 a.full = dfixed_const(256 * 13);
340 chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
341 a.full = dfixed_const(10);
342 chunk_time.full = dfixed_div(chunk_time, a);
343
344 /* Determine the worst case latency
345 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
346 * WorstCaseLatency = worst case time from urgent to when the MC starts
347 * to return data
348 * READ_DELAY_IDLE_MAX = constant of 1us
349 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
350 * which consists of pipeline delay and inter chunk gap
351 */
352 if (dfixed_trunc(wm->num_line_pair) > 1) {
353 a.full = dfixed_const(3);
354 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
355 wm->worst_case_latency.full += read_delay_latency.full;
356 } else {
357 a.full = dfixed_const(2);
358 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
359 wm->worst_case_latency.full += read_delay_latency.full;
360 }
361
362 /* Determine the tolerable latency
363 * TolerableLatency = Any given request has only 1 line time
364 * for the data to be returned
365 * LBRequestFifoDepth = Number of chunk requests the LB can
366 * put into the request FIFO for a display
367 * LineTime = total time for one line of display
368 * ChunkTime = the time it takes the DCP to send one chunk
369 * of data to the LB which consists of
370 * pipeline delay and inter chunk gap
371 */
372 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
373 tolerable_latency.full = line_time.full;
374 } else {
375 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
376 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
377 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
378 tolerable_latency.full = line_time.full - tolerable_latency.full;
379 }
380 /* We assume worst case 32bits (4 bytes) */
381 wm->dbpp.full = dfixed_const(4 * 8);
382
383 /* Determine the maximum priority mark
384 * width = viewport width in pixels
385 */
386 a.full = dfixed_const(16);
387 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
388 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
389 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
390
391 /* Determine estimated width */
392 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
393 estimated_width.full = dfixed_div(estimated_width, consumption_time);
394 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
395 wm->priority_mark.full = dfixed_const(10);
396 } else {
397 a.full = dfixed_const(16);
398 wm->priority_mark.full = dfixed_div(estimated_width, a);
399 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
400 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
401 }
402 }
403
rs690_bandwidth_update(struct radeon_device * rdev)404 void rs690_bandwidth_update(struct radeon_device *rdev)
405 {
406 struct drm_display_mode *mode0 = NULL;
407 struct drm_display_mode *mode1 = NULL;
408 struct rs690_watermark wm0;
409 struct rs690_watermark wm1;
410 u32 tmp;
411 u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
412 u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
413 fixed20_12 priority_mark02, priority_mark12, fill_rate;
414 fixed20_12 a, b;
415
416 radeon_update_display_priority(rdev);
417
418 if (rdev->mode_info.crtcs[0]->base.enabled)
419 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
420 if (rdev->mode_info.crtcs[1]->base.enabled)
421 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
422 /*
423 * Set display0/1 priority up in the memory controller for
424 * modes if the user specifies HIGH for displaypriority
425 * option.
426 */
427 if ((rdev->disp_priority == 2) &&
428 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
429 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
430 tmp &= C_000104_MC_DISP0R_INIT_LAT;
431 tmp &= C_000104_MC_DISP1R_INIT_LAT;
432 if (mode0)
433 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
434 if (mode1)
435 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
436 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
437 }
438 rs690_line_buffer_adjust(rdev, mode0, mode1);
439
440 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
441 WREG32(R_006C9C_DCP_CONTROL, 0);
442 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
443 WREG32(R_006C9C_DCP_CONTROL, 2);
444
445 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
446 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
447
448 tmp = (wm0.lb_request_fifo_depth - 1);
449 tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
450 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
451
452 if (mode0 && mode1) {
453 if (dfixed_trunc(wm0.dbpp) > 64)
454 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
455 else
456 a.full = wm0.num_line_pair.full;
457 if (dfixed_trunc(wm1.dbpp) > 64)
458 b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
459 else
460 b.full = wm1.num_line_pair.full;
461 a.full += b.full;
462 fill_rate.full = dfixed_div(wm0.sclk, a);
463 if (wm0.consumption_rate.full > fill_rate.full) {
464 b.full = wm0.consumption_rate.full - fill_rate.full;
465 b.full = dfixed_mul(b, wm0.active_time);
466 a.full = dfixed_mul(wm0.worst_case_latency,
467 wm0.consumption_rate);
468 a.full = a.full + b.full;
469 b.full = dfixed_const(16 * 1000);
470 priority_mark02.full = dfixed_div(a, b);
471 } else {
472 a.full = dfixed_mul(wm0.worst_case_latency,
473 wm0.consumption_rate);
474 b.full = dfixed_const(16 * 1000);
475 priority_mark02.full = dfixed_div(a, b);
476 }
477 if (wm1.consumption_rate.full > fill_rate.full) {
478 b.full = wm1.consumption_rate.full - fill_rate.full;
479 b.full = dfixed_mul(b, wm1.active_time);
480 a.full = dfixed_mul(wm1.worst_case_latency,
481 wm1.consumption_rate);
482 a.full = a.full + b.full;
483 b.full = dfixed_const(16 * 1000);
484 priority_mark12.full = dfixed_div(a, b);
485 } else {
486 a.full = dfixed_mul(wm1.worst_case_latency,
487 wm1.consumption_rate);
488 b.full = dfixed_const(16 * 1000);
489 priority_mark12.full = dfixed_div(a, b);
490 }
491 if (wm0.priority_mark.full > priority_mark02.full)
492 priority_mark02.full = wm0.priority_mark.full;
493 if (dfixed_trunc(priority_mark02) < 0)
494 priority_mark02.full = 0;
495 if (wm0.priority_mark_max.full > priority_mark02.full)
496 priority_mark02.full = wm0.priority_mark_max.full;
497 if (wm1.priority_mark.full > priority_mark12.full)
498 priority_mark12.full = wm1.priority_mark.full;
499 if (dfixed_trunc(priority_mark12) < 0)
500 priority_mark12.full = 0;
501 if (wm1.priority_mark_max.full > priority_mark12.full)
502 priority_mark12.full = wm1.priority_mark_max.full;
503 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
504 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
505 if (rdev->disp_priority == 2) {
506 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
507 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
508 }
509 } else if (mode0) {
510 if (dfixed_trunc(wm0.dbpp) > 64)
511 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
512 else
513 a.full = wm0.num_line_pair.full;
514 fill_rate.full = dfixed_div(wm0.sclk, a);
515 if (wm0.consumption_rate.full > fill_rate.full) {
516 b.full = wm0.consumption_rate.full - fill_rate.full;
517 b.full = dfixed_mul(b, wm0.active_time);
518 a.full = dfixed_mul(wm0.worst_case_latency,
519 wm0.consumption_rate);
520 a.full = a.full + b.full;
521 b.full = dfixed_const(16 * 1000);
522 priority_mark02.full = dfixed_div(a, b);
523 } else {
524 a.full = dfixed_mul(wm0.worst_case_latency,
525 wm0.consumption_rate);
526 b.full = dfixed_const(16 * 1000);
527 priority_mark02.full = dfixed_div(a, b);
528 }
529 if (wm0.priority_mark.full > priority_mark02.full)
530 priority_mark02.full = wm0.priority_mark.full;
531 if (dfixed_trunc(priority_mark02) < 0)
532 priority_mark02.full = 0;
533 if (wm0.priority_mark_max.full > priority_mark02.full)
534 priority_mark02.full = wm0.priority_mark_max.full;
535 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
536 if (rdev->disp_priority == 2)
537 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
538 } else if (mode1) {
539 if (dfixed_trunc(wm1.dbpp) > 64)
540 a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
541 else
542 a.full = wm1.num_line_pair.full;
543 fill_rate.full = dfixed_div(wm1.sclk, a);
544 if (wm1.consumption_rate.full > fill_rate.full) {
545 b.full = wm1.consumption_rate.full - fill_rate.full;
546 b.full = dfixed_mul(b, wm1.active_time);
547 a.full = dfixed_mul(wm1.worst_case_latency,
548 wm1.consumption_rate);
549 a.full = a.full + b.full;
550 b.full = dfixed_const(16 * 1000);
551 priority_mark12.full = dfixed_div(a, b);
552 } else {
553 a.full = dfixed_mul(wm1.worst_case_latency,
554 wm1.consumption_rate);
555 b.full = dfixed_const(16 * 1000);
556 priority_mark12.full = dfixed_div(a, b);
557 }
558 if (wm1.priority_mark.full > priority_mark12.full)
559 priority_mark12.full = wm1.priority_mark.full;
560 if (dfixed_trunc(priority_mark12) < 0)
561 priority_mark12.full = 0;
562 if (wm1.priority_mark_max.full > priority_mark12.full)
563 priority_mark12.full = wm1.priority_mark_max.full;
564 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
565 if (rdev->disp_priority == 2)
566 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
567 }
568
569 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
570 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
571 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
572 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
573 }
574
rs690_mc_rreg(struct radeon_device * rdev,uint32_t reg)575 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
576 {
577 uint32_t r;
578
579 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
580 r = RREG32(R_00007C_MC_DATA);
581 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
582 return r;
583 }
584
rs690_mc_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)585 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
586 {
587 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
588 S_000078_MC_IND_WR_EN(1));
589 WREG32(R_00007C_MC_DATA, v);
590 WREG32(R_000078_MC_INDEX, 0x7F);
591 }
592
rs690_mc_program(struct radeon_device * rdev)593 static void rs690_mc_program(struct radeon_device *rdev)
594 {
595 struct rv515_mc_save save;
596
597 /* Stops all mc clients */
598 rv515_mc_stop(rdev, &save);
599
600 /* Wait for mc idle */
601 if (rs690_mc_wait_for_idle(rdev))
602 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
603 /* Program MC, should be a 32bits limited address space */
604 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
605 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
606 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
607 WREG32(R_000134_HDP_FB_LOCATION,
608 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
609
610 rv515_mc_resume(rdev, &save);
611 }
612
rs690_startup(struct radeon_device * rdev)613 static int rs690_startup(struct radeon_device *rdev)
614 {
615 int r;
616
617 rs690_mc_program(rdev);
618 /* Resume clock */
619 rv515_clock_startup(rdev);
620 /* Initialize GPU configuration (# pipes, ...) */
621 rs690_gpu_init(rdev);
622 /* Initialize GART (initialize after TTM so we can allocate
623 * memory through TTM but finalize after TTM) */
624 r = rs400_gart_enable(rdev);
625 if (r)
626 return r;
627
628 /* allocate wb buffer */
629 r = radeon_wb_init(rdev);
630 if (r)
631 return r;
632
633 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
634 if (r) {
635 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
636 return r;
637 }
638
639 /* Enable IRQ */
640 rs600_irq_set(rdev);
641 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
642 /* 1M ring buffer */
643 r = r100_cp_init(rdev, 1024 * 1024);
644 if (r) {
645 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
646 return r;
647 }
648
649 r = radeon_ib_pool_init(rdev);
650 if (r) {
651 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
652 return r;
653 }
654
655 r = r600_audio_init(rdev);
656 if (r) {
657 dev_err(rdev->dev, "failed initializing audio\n");
658 return r;
659 }
660
661 return 0;
662 }
663
rs690_resume(struct radeon_device * rdev)664 int rs690_resume(struct radeon_device *rdev)
665 {
666 int r;
667
668 /* Make sur GART are not working */
669 rs400_gart_disable(rdev);
670 /* Resume clock before doing reset */
671 rv515_clock_startup(rdev);
672 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
673 if (radeon_asic_reset(rdev)) {
674 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
675 RREG32(R_000E40_RBBM_STATUS),
676 RREG32(R_0007C0_CP_STAT));
677 }
678 /* post */
679 atom_asic_init(rdev->mode_info.atom_context);
680 /* Resume clock after posting */
681 rv515_clock_startup(rdev);
682 /* Initialize surface registers */
683 radeon_surface_init(rdev);
684
685 rdev->accel_working = true;
686 r = rs690_startup(rdev);
687 if (r) {
688 rdev->accel_working = false;
689 }
690 return r;
691 }
692
rs690_suspend(struct radeon_device * rdev)693 int rs690_suspend(struct radeon_device *rdev)
694 {
695 r600_audio_fini(rdev);
696 r100_cp_disable(rdev);
697 radeon_wb_disable(rdev);
698 rs600_irq_disable(rdev);
699 rs400_gart_disable(rdev);
700 return 0;
701 }
702
rs690_fini(struct radeon_device * rdev)703 void rs690_fini(struct radeon_device *rdev)
704 {
705 r600_audio_fini(rdev);
706 r100_cp_fini(rdev);
707 radeon_wb_fini(rdev);
708 radeon_ib_pool_fini(rdev);
709 radeon_gem_fini(rdev);
710 rs400_gart_fini(rdev);
711 radeon_irq_kms_fini(rdev);
712 radeon_fence_driver_fini(rdev);
713 radeon_bo_fini(rdev);
714 radeon_atombios_fini(rdev);
715 free(rdev->bios, DRM_MEM_DRIVER);
716 rdev->bios = NULL;
717 }
718
rs690_init(struct radeon_device * rdev)719 int rs690_init(struct radeon_device *rdev)
720 {
721 int r;
722
723 /* Disable VGA */
724 rv515_vga_render_disable(rdev);
725 /* Initialize scratch registers */
726 radeon_scratch_init(rdev);
727 /* Initialize surface registers */
728 radeon_surface_init(rdev);
729 /* restore some register to sane defaults */
730 r100_restore_sanity(rdev);
731 /* TODO: disable VGA need to use VGA request */
732 /* BIOS*/
733 if (!radeon_get_bios(rdev)) {
734 if (ASIC_IS_AVIVO(rdev))
735 return -EINVAL;
736 }
737 if (rdev->is_atom_bios) {
738 r = radeon_atombios_init(rdev);
739 if (r)
740 return r;
741 } else {
742 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
743 return -EINVAL;
744 }
745 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
746 if (radeon_asic_reset(rdev)) {
747 dev_warn(rdev->dev,
748 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
749 RREG32(R_000E40_RBBM_STATUS),
750 RREG32(R_0007C0_CP_STAT));
751 }
752 /* check if cards are posted or not */
753 if (radeon_boot_test_post_card(rdev) == false)
754 return -EINVAL;
755
756 /* Initialize clocks */
757 radeon_get_clock_info(rdev->ddev);
758 /* initialize memory controller */
759 rs690_mc_init(rdev);
760 rv515_debugfs(rdev);
761 /* Fence driver */
762 r = radeon_fence_driver_init(rdev);
763 if (r)
764 return r;
765 r = radeon_irq_kms_init(rdev);
766 if (r)
767 return r;
768 /* Memory manager */
769 r = radeon_bo_init(rdev);
770 if (r)
771 return r;
772 r = rs400_gart_init(rdev);
773 if (r)
774 return r;
775 rs600_set_safe_registers(rdev);
776
777 rdev->accel_working = true;
778 r = rs690_startup(rdev);
779 if (r) {
780 /* Somethings want wront with the accel init stop accel */
781 dev_err(rdev->dev, "Disabling GPU acceleration\n");
782 r100_cp_fini(rdev);
783 radeon_wb_fini(rdev);
784 radeon_ib_pool_fini(rdev);
785 rs400_gart_fini(rdev);
786 radeon_irq_kms_fini(rdev);
787 rdev->accel_working = false;
788 }
789 return 0;
790 }
791