1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2009-2012 Semihalf 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: stable/12/sys/dev/nand/nandsim.h 326255 2017-11-27 14:52:40Z pfg $ 29 */ 30 31 #ifndef _NANDSIM_H_ 32 #define _NANDSIM_H_ 33 34 #include <sys/ioccom.h> 35 #include <sys/types.h> 36 37 #define MAX_SIM_DEV 4 38 #define MAX_CTRL_CS 4 39 #define MAX_ECC_BYTES 512 40 #define MAX_BAD_BLOCKS 512 41 #define DEV_MODEL_STR_SIZE 21 42 #define MAN_STR_SIZE 13 43 #define FILENAME_SIZE 20 44 45 #define MAX_CHIPS (MAX_SIM_DEV*MAX_CTRL_CS) 46 47 #define NANDSIM_OUTPUT_NONE 0x0 48 #define NANDSIM_OUTPUT_CONSOLE 0x1 49 #define NANDSIM_OUTPUT_RAM 0x2 50 #define NANDSIM_OUTPUT_FILE 0x3 51 52 struct sim_ctrl_chip { 53 uint8_t ctrl_num; 54 uint8_t chip_num; 55 }; 56 57 #define NANDSIM_BASE 'A' 58 59 struct sim_param { 60 uint8_t log_level; 61 uint8_t log_output; 62 }; 63 64 #define NANDSIM_SIM_PARAM _IOW(NANDSIM_BASE, 1, struct sim_param) 65 66 struct sim_ctrl { 67 uint8_t running; 68 uint8_t created; 69 uint8_t num; 70 uint8_t num_cs; 71 uint8_t ecc; 72 char filename[FILENAME_SIZE]; 73 uint16_t ecc_layout[MAX_ECC_BYTES]; 74 }; 75 #define NANDSIM_CREATE_CTRL _IOW(NANDSIM_BASE, 2, struct sim_ctrl) 76 #define NANDSIM_DESTROY_CTRL _IOW(NANDSIM_BASE, 3, int) 77 78 struct sim_chip { 79 uint8_t num; 80 uint8_t ctrl_num; 81 uint8_t created; 82 uint8_t device_id; 83 uint8_t manufact_id; 84 char device_model[DEV_MODEL_STR_SIZE]; 85 char manufacturer[MAN_STR_SIZE]; 86 uint8_t col_addr_cycles; 87 uint8_t row_addr_cycles; 88 uint8_t features; 89 uint8_t width; 90 uint32_t page_size; 91 uint32_t oob_size; 92 uint32_t pgs_per_blk; 93 uint32_t blks_per_lun; 94 uint32_t luns; 95 96 uint32_t prog_time; 97 uint32_t erase_time; 98 uint32_t read_time; 99 uint32_t ccs_time; 100 101 uint32_t error_ratio; 102 uint32_t wear_level; 103 uint32_t bad_block_map[MAX_BAD_BLOCKS]; 104 uint8_t is_wp; 105 }; 106 107 #define NANDSIM_CREATE_CHIP _IOW(NANDSIM_BASE, 3, struct sim_chip) 108 109 struct sim_chip_destroy { 110 uint8_t ctrl_num; 111 uint8_t chip_num; 112 }; 113 #define NANDSIM_DESTROY_CHIP _IOW(NANDSIM_BASE, 4, struct sim_chip_destroy) 114 115 #define NANDSIM_START_CTRL _IOW(NANDSIM_BASE, 5, int) 116 #define NANDSIM_STOP_CTRL _IOW(NANDSIM_BASE, 6, int) 117 #define NANDSIM_RESTART_CTRL _IOW(NANDSIM_BASE, 7, int) 118 119 #define NANDSIM_STATUS_CTRL _IOWR(NANDSIM_BASE, 8, struct sim_ctrl) 120 #define NANDSIM_STATUS_CHIP _IOWR(NANDSIM_BASE, 9, struct sim_chip) 121 122 struct sim_mod { 123 uint8_t chip_num; 124 uint8_t ctrl_num; 125 uint32_t field; 126 uint32_t new_value; 127 }; 128 #define SIM_MOD_LOG_LEVEL 0 129 #define SIM_MOD_ERASE_TIME 1 130 #define SIM_MOD_PROG_TIME 2 131 #define SIM_MOD_READ_TIME 3 132 #define SIM_MOD_CCS_TIME 4 133 #define SIM_MOD_ERROR_RATIO 5 134 135 #define NANDSIM_MODIFY _IOW(NANDSIM_BASE, 10, struct sim_mod) 136 #define NANDSIM_FREEZE _IOW(NANDSIM_BASE, 11, struct sim_ctrl_chip) 137 138 struct sim_error { 139 uint8_t ctrl_num; 140 uint8_t chip_num; 141 uint32_t page_num; 142 uint32_t column; 143 uint32_t len; 144 uint32_t pattern; 145 }; 146 #define NANDSIM_INJECT_ERROR _IOW(NANDSIM_BASE, 20, struct sim_error) 147 148 #define NANDSIM_GOOD_BLOCK 0 149 #define NANDSIM_BAD_BLOCK 1 150 struct sim_block_state { 151 uint8_t ctrl_num; 152 uint8_t chip_num; 153 uint32_t block_num; 154 int wearout; 155 uint8_t state; 156 }; 157 #define NANDSIM_SET_BLOCK_STATE _IOW(NANDSIM_BASE, 21, struct sim_block_state) 158 #define NANDSIM_GET_BLOCK_STATE _IOWR(NANDSIM_BASE, 22, struct sim_block_state) 159 160 struct sim_log { 161 uint8_t ctrl_num; 162 char* log; 163 size_t len; 164 }; 165 #define NANDSIM_PRINT_LOG _IOWR(NANDSIM_BASE, 23, struct sim_log) 166 167 struct sim_dump { 168 uint8_t ctrl_num; 169 uint8_t chip_num; 170 uint32_t block_num; 171 uint32_t len; 172 void* data; 173 }; 174 #define NANDSIM_DUMP _IOWR(NANDSIM_BASE, 24, struct sim_dump) 175 #define NANDSIM_RESTORE _IOWR(NANDSIM_BASE, 25, struct sim_dump) 176 177 #endif /* _NANDSIM_H_ */ 178