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Searched refs:clk_ctrl (Results 1 – 2 of 2) sorted by relevance

/trueos/sys/mips/atheros/
HDar934x_chip.c92 uint32_t pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_chip_detect_sys_frequency() local
156 clk_ctrl = ATH_READ_REG(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); in ar934x_chip_detect_sys_frequency()
158 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & in ar934x_chip_detect_sys_frequency()
161 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) in ar934x_chip_detect_sys_frequency()
163 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) in ar934x_chip_detect_sys_frequency()
168 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & in ar934x_chip_detect_sys_frequency()
171 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_chip_detect_sys_frequency()
173 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) in ar934x_chip_detect_sys_frequency()
178 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & in ar934x_chip_detect_sys_frequency()
181 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) in ar934x_chip_detect_sys_frequency()
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/trueos/sys/dev/bwi/
HDif_bwi.c1121 uint32_t clk_ctrl, clk_src; in bwi_set_clock_mode() local
1145 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); in bwi_set_clock_mode()
1146 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); in bwi_set_clock_mode()
1150 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; in bwi_set_clock_mode()
1151 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; in bwi_set_clock_mode()
1154 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; in bwi_set_clock_mode()
1157 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | in bwi_set_clock_mode()
1161 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; in bwi_set_clock_mode()
1166 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); in bwi_set_clock_mode()