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Searched refs:RL_IMR (Results 1 – 3 of 3) sorted by relevance

/trueos/sys/pci/
HDif_rl.c1511 CSR_WRITE_2(sc, RL_IMR, 0); in rl_intr()
1537 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); in rl_intr()
1749 CSR_WRITE_2(sc, RL_IMR, 0); in rl_init_locked()
1753 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); in rl_init_locked()
1855 CSR_WRITE_2(sc, RL_IMR, 0x0000); in rl_ioctl()
1866 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); in rl_ioctl()
1926 CSR_WRITE_2(sc, RL_IMR, 0x0000); in rl_stop()
HDif_rlreg.h70 #define RL_IMR 0x003C /* interrupt mask register */ macro
/trueos/sys/dev/re/
HDif_re.c2550 CSR_WRITE_2(sc, RL_IMR, 0); in re_intr()
2624 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); in re_int_task()
2645 CSR_WRITE_2(sc, RL_IMR, 0); in re_intr_msi()
2703 CSR_WRITE_2(sc, RL_IMR, intrs); in re_intr_msi()
3233 CSR_WRITE_2(sc, RL_IMR, 0); in re_init_locked()
3241 CSR_WRITE_2(sc, RL_IMR, 0); in re_init_locked()
3243 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); in re_init_locked()
3445 CSR_WRITE_2(sc, RL_IMR, 0x0000); in re_ioctl()
3452 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); in re_ioctl()
3614 CSR_WRITE_2(sc, RL_IMR, 0x0000); in re_stop()