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Searched refs:PIPE_VBLANK_INTERRUPT_STATUS (Results 1 – 4 of 4) sorted by relevance

/trueos/sys/dev/drm2/i915/
HDi915_irq.c484 PIPE_VBLANK_INTERRUPT_STATUS; in valleyview_irq_handler()
1667 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS && in i8xx_irq_handler()
1676 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS && in i8xx_irq_handler()
1862 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && in i915_irq_handler()
HDi915_reg.h2594 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) macro
HDintel_display.c848 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); in intel_wait_for_vblank()
852 I915_READ(pipestat_reg) & PIPE_VBLANK_INTERRUPT_STATUS, in intel_wait_for_vblank()
/trueos/sys/dev/drm/
HDi915_reg.h1351 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) macro