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Searched refs:regCP_HQD_GFX_STATUS (Results 1 – 7 of 7) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_4_3_offset.h3270 #define regCP_HQD_GFX_STATUS … macro
Dgc_9_4_2_offset.h681 #define regCP_HQD_GFX_STATUS … macro
Dgc_11_5_0_offset.h3427 #define regCP_HQD_GFX_STATUS … macro
Dgc_12_0_0_offset.h3734 #define regCP_HQD_GFX_STATUS … macro
Dgc_11_0_3_offset.h4678 #define regCP_HQD_GFX_STATUS … macro
Dgc_11_0_0_offset.h4454 #define regCP_HQD_GFX_STATUS … macro
/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dgfx_v9_4_3.c158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS),