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Searched refs:regCP_GFX_HQD_HQ_STATUS0 (Results 1 – 6 of 6) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_offset.h3419 #define regCP_GFX_HQD_HQ_STATUS0 … macro
Dgc_12_0_0_offset.h3726 #define regCP_GFX_HQD_HQ_STATUS0 … macro
Dgc_11_0_3_offset.h4670 #define regCP_GFX_HQD_HQ_STATUS0 … macro
Dgc_11_0_0_offset.h4446 #define regCP_GFX_HQD_HQ_STATUS0 … macro
/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dgfx_v12_0.c193 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),
Dgfx_v11_0.c233 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),