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Searched refs:imm6 (Results 1 – 15 of 15) sorted by relevance

/openbsd/src/sys/arch/arm64/arm64/
Ddisasm.c788 uint64_t sf, uint64_t shift, uint64_t Rm, uint64_t imm6, in shiftreg_common() argument
792 if ((sf == 0) && (imm6 >= 32)) { in shiftreg_common()
814 if (imm6 != 0) in shiftreg_common()
815 PRINTF(", %s #%u", DecodeShift(shift), (u_int)imm6); in shiftreg_common()
1076 OP6FUNC(op_add_shiftreg, sf, shift, Rm, imm6, Rn, Rd) in OP6FUNC() argument
1082 shiftreg_common(di, pc, insn, sf, shift, Rm, imm6, Rn, Rd, in OP6FUNC()
1100 OP6FUNC(op_adds_shiftreg, sf, shift, Rm, imm6, Rn, Rd) in OP6FUNC() argument
1107 shiftreg_common(di, pc, insn, sf, shift, Rm, imm6, Rn, Rd, in OP6FUNC()
1142 OP6FUNC(op_and_shiftreg, sf, shift, Rm, imm6, Rn, Rd) in OP6FUNC() argument
1144 shiftreg_common(di, pc, insn, sf, shift, Rm, imm6, Rn, Rd, in OP6FUNC()
[all …]
/openbsd/src/gnu/usr.bin/binutils-2.17/gas/config/
Dbfin-parse.y214 #define imm6(x) EXPR_VALUE (x) macro
1874 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
2011 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2065 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2088 $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2233 $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2243 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
/openbsd/src/gnu/usr.bin/binutils-2.17/cpu/
Dsh64-media.cpu99 (df f-imm6 "Immediate value (6 bits)" ((ISA media)) 15 6 INT #f #f)
172 (dshmop imm6 "Immediate (6 bits)" () h-sint f-imm6)
249 "beqi$likely $rm, $imm6, $tra"
250 (+ (f-op 57) rm (f-ext 1) imm6 likely (f-8-2 0) tra (f-rsvd 0))
251 (if (eq rm (ext DI imm6))
299 "bnei$likely $rm, $imm6, $tra"
301 (if (ne rm (ext DI imm6))
1730 "xori $rm, $imm6, $rd"
1732 (set rd (xor rm (ext DI imm6))))
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMInstrNEON.td4020 let Inst{21-19} = 0b001; // imm6 = 001xxx
4024 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4028 let Inst{21} = 0b1; // imm6 = 1xxxxx
4032 // imm6 = xxxxxx
4037 let Inst{21-19} = 0b001; // imm6 = 001xxx
4041 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4045 let Inst{21} = 0b1; // imm6 = 1xxxxx
4049 // imm6 = xxxxxx
4057 let Inst{21-19} = 0b001; // imm6 = 001xxx
4061 let Inst{21-20} = 0b01; // imm6 = 01xxxx
[all …]
DARMInstrFormats.td312 // other shift immediates. The imm6 field is encoded like so:
315 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
316 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
317 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
318 // 64 64 - <imm> is encoded in imm6<5:0>
DARMInstrMVE.td3888 (outs MQPR:$Qd), (ins MQPR:$Qm, imm_operand_type:$imm6),
3889 "$Qd, $Qm, $imm6", vpred_r, "", !if(fsi, 0b10, 0b01), []> {
3891 bits<6> imm6;
3897 let Inst{19-16} = imm6{3-0};
3924 let Inst{20} = imm6{4};
/openbsd/src/gnu/llvm/lld/ELF/Arch/
DRISCV.cpp343 uint16_t imm6 = extractBits(val, 6, 6) << 7; in relocate() local
347 insn |= imm11 | imm4 | imm9_8 | imm10 | imm6 | imm7 | imm3_1 | imm5; in relocate()
/openbsd/src/gnu/usr.bin/binutils-2.17/gas/
Dbfin-parse.c605 #define imm6(x) EXPR_VALUE (x) macro
4216 …(yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), imm6 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yy…
4370 (yyval.instr) = DSP32SHIFTIMM (3, 0, -imm6 ((yyvsp[0].expr)), 0, 0, IS_A1 ((yyvsp[-3].reg)));
4435 (yyval.instr) = DSP32SHIFTIMM (3, 0, -imm6 ((yyvsp[0].expr)), 0, 1, IS_A1 ((yyvsp[-3].reg)));
4460 …(yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), -imm6 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), 2,…
4628 (yyval.instr) = DSP32SHIFTIMM (3, 0, imm6 ((yyvsp[0].expr)), 0, 2, IS_A1 ((yyvsp[-4].reg)));
4640 …(yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), imm6 ((yyvsp[0].expr)), &(yyvsp[-2].reg), 3, I…
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DSVEInstrFormats.td2611 : I<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, simm6_32b:$imm6),
2612 asm, "\t$Rd, $Rn, $imm6",
2617 bits<6> imm6;
2624 let Inst{10-5} = imm6;
2629 : I<(outs GPR64:$Rd), (ins simm6_32b:$imm6),
2630 asm, "\t$Rd, $imm6",
2634 bits<6> imm6;
2641 let Inst{10-5} = imm6;
7060 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6),
7061 asm, "\t$Zt, $Pg/z, [$Rn, $imm6]",
[all …]
DAArch64InstrFormats.td1039 // {5-0} - imm6
1069 // {5-0} - imm6
1099 // {5-0} - imm6: #0, #8, #16, or #24
1108 // {5-0} - imm6: #0 or #8
1138 // {5-0} - imm6: #0 or #12
2902 isSub, 0, GPR64sp, asm_inst, "\t$Rd, $Rn, $imm6, $imm4",
2903 (ins GPR64sp:$Rn, uimm6s16:$imm6, imm0_15:$imm4),
2904 (set GPR64sp:$Rd, (OpNode GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4))> {
2905 bits<6> imm6;
2909 let Inst{21-16} = imm6;
DAArch64InstrInfo.td2115 def : Pat<(int_aarch64_addg (am_indexedu6s128 GPR64sp:$Rn, uimm6s16:$imm6), imm0_15:$imm4),
2116 (ADDG GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4)>;
2159 : Pseudo<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, uimm6s16:$imm6, GPR64sp:$Rm, imm0_15:$imm4), []>,
/openbsd/src/gnu/usr.bin/binutils-2.17/opcodes/
Dbfin-dis.c392 #define imm6(x) fmtconst (c_imm6, x, 0, outf) macro
4082 OUTS (outf, imm6 (immag)); in decode_dsp32shiftimm_0()
4117 OUTS (outf, imm6 (immag)); in decode_dsp32shiftimm_0()
4195 OUTS (outf, imm6 (immag)); in decode_dsp32shiftimm_0()
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp6930 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); in DecodeMVEVCVTt1fp() local
6936 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) in DecodeMVEVCVTt1fp()
/openbsd/src/gnu/llvm/llvm/lib/Target/AVR/
DAVRInstrInfo.td245 // Addressing mode pattern reg+imm6
/openbsd/src/gnu/llvm/lldb/source/Plugins/Instruction/ARM/
DEmulateInstructionARM.cpp2839 uint32_t imm6 = Bits32(opcode, 21, 16); in EmulateB() local
2844 (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); in EmulateB()