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Searched refs:ih1 (Results 1 – 10 of 10) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dih_v6_0.c65 if (adev->irq.ih1.ring_size) { in ih_v6_0_init_register_offset()
66 ih_regs = &adev->irq.ih1.ih_regs; in ih_v6_0_init_register_offset()
200 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v6_0_toggle_interrupts()
281 if (ih == &adev->irq.ih1) { in ih_v6_0_enable_ring()
323 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v6_0_irq_init()
378 if (adev->irq.ih1.ring_size) { in ih_v6_0_irq_init()
543 *adev->irq.ih1.wptr_cpu = wptr; in ih_v6_0_self_irq()
596 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE, in ih_v6_0_sw_init()
601 adev->irq.ih1.use_doorbell = true; in ih_v6_0_sw_init()
602 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; in ih_v6_0_sw_init()
Dih_v6_1.c65 if (adev->irq.ih1.ring_size) { in ih_v6_1_init_register_offset()
66 ih_regs = &adev->irq.ih1.ih_regs; in ih_v6_1_init_register_offset()
172 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v6_1_toggle_interrupts()
253 if (ih == &adev->irq.ih1) { in ih_v6_1_enable_ring()
295 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v6_1_irq_init()
350 if (adev->irq.ih1.ring_size) { in ih_v6_1_irq_init()
516 *adev->irq.ih1.wptr_cpu = wptr; in ih_v6_1_self_irq()
575 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE, in ih_v6_1_sw_init()
580 adev->irq.ih1.use_doorbell = true; in ih_v6_1_sw_init()
581 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; in ih_v6_1_sw_init()
Dih_v7_0.c65 if (adev->irq.ih1.ring_size) { in ih_v7_0_init_register_offset()
66 ih_regs = &adev->irq.ih1.ih_regs; in ih_v7_0_init_register_offset()
172 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v7_0_toggle_interrupts()
253 if (ih == &adev->irq.ih1) { in ih_v7_0_enable_ring()
295 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v7_0_irq_init()
350 if (adev->irq.ih1.ring_size) { in ih_v7_0_irq_init()
513 *adev->irq.ih1.wptr_cpu = wptr; in ih_v7_0_self_irq()
565 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE, in ih_v7_0_sw_init()
570 adev->irq.ih1.use_doorbell = true; in ih_v7_0_sw_init()
571 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; in ih_v7_0_sw_init()
Dvega10_ih.c64 if (adev->irq.ih1.ring_size) { in vega10_ih_init_register_offset()
65 ih_regs = &adev->irq.ih1.ih_regs; in vega10_ih_init_register_offset()
143 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; in vega10_ih_toggle_interrupts()
224 if (ih == &adev->irq.ih1) in vega10_ih_enable_ring()
263 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; in vega10_ih_irq_init()
502 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); in vega10_ih_sw_init()
506 adev->irq.ih1.use_doorbell = true; in vega10_ih_sw_init()
507 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; in vega10_ih_sw_init()
Dvega20_ih.c72 if (adev->irq.ih1.ring_size) { in vega20_ih_init_register_offset()
73 ih_regs = &adev->irq.ih1.ih_regs; in vega20_ih_init_register_offset()
179 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; in vega20_ih_toggle_interrupts()
260 if (ih == &adev->irq.ih1) in vega20_ih_enable_ring()
309 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; in vega20_ih_irq_init()
587 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, use_bus_addr); in vega20_ih_sw_init()
591 adev->irq.ih1.use_doorbell = true; in vega20_ih_sw_init()
592 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; in vega20_ih_sw_init()
Dnavi10_ih.c66 if (adev->irq.ih1.ring_size) { in navi10_ih_init_register_offset()
67 ih_regs = &adev->irq.ih1.ih_regs; in navi10_ih_init_register_offset()
198 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; in navi10_ih_toggle_interrupts()
279 if (ih == &adev->irq.ih1) in navi10_ih_enable_ring()
319 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; in navi10_ih_irq_init()
581 adev->irq.ih1.ring_size = 0; in navi10_ih_sw_init()
Damdgpu_irq.h92 struct amdgpu_ih_ring ih, ih1, ih2, ih_soft; member
Damdgpu_irq.c194 amdgpu_ih_process(adev, &adev->irq.ih1); in amdgpu_irq_handle_ih1()
348 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); in amdgpu_irq_fini_hw()
Damdgpu_gmc.c486 ih = &adev->irq.ih1; in amdgpu_gmc_filter_faults_remove()
/openbsd/src/sys/dev/pci/drm/amd/amdkfd/
Dkfd_svm.c2306 &pdd->dev->adev->irq.ih1); in svm_range_drain_retry_fault()
2494 if (adev->irq.ih1.ring_size) { in svm_range_unmap_from_cpu()
2495 ih = &adev->irq.ih1; in svm_range_unmap_from_cpu()