| /openbsd/src/gnu/llvm/llvm/lib/Target/XCore/ |
| D | XCoreMachineFunctionInfo.cpp | 53 TRI.getSpillAlign(RC), true); in createLRSpillSlot()
67 MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), true); in createFPSpillSlot()
80 Align Alignment = TRI.getSpillAlign(RC); in createEHSpillSlot()
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| D | XCoreFrameLowering.cpp | 580 Align Alignment = TRI.getSpillAlign(RC); in processFunctionBeforeFrameFinalized()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Mips/ |
| D | MipsMachineFunction.cpp | 165 TRI.getSpillAlign(RC), false); in createEhDataRegsFI()
179 TRI.getSpillAlign(RC), false); in createISRRegFI()
205 TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC), false); in getMoveF64ViaSpillFI()
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| D | MipsSEFrameLowering.cpp | 898 TRI->getSpillAlign(RC), false); in determineCalleeSaves()
914 TRI->getSpillAlign(RC), false); in determineCalleeSaves()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86LowerTileCopy.cpp | 91 Align Alignment = TRI->getSpillAlign(X86::TILERegClass); in runOnMachineFunction()
95 Alignment = TRI->getSpillAlign(X86::GR64RegClass); in runOnMachineFunction()
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| D | X86FastPreTileConfig.cpp | 129 Align Alignment = TRI->getSpillAlign(RC); in getStackSpaceFor()
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| D | X86FrameLowering.cpp | 2746 Align Alignment = TRI->getSpillAlign(*RC); in assignCalleeSavedSpillSlots()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| D | HexagonVExtract.cpp | 140 Align Alignment = HRI.getSpillAlign(VecRC); in runOnMachineFunction()
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| D | HexagonFrameLowering.cpp | 1680 Align Alignment = std::min(TRI->getSpillAlign(*RC), getStackAlign()); in assignCalleeSavedSpillSlots()
1903 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandStoreVec2()
1950 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandLoadVec2()
1989 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandStoreVec()
2017 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandLoadVec()
2120 Align A = HRI.getSpillAlign(*RC); in determineCalleeSaves()
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| D | HexagonInstrInfo.cpp | 1174 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1190 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1212 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1229 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
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| D | HexagonISelLowering.cpp | 526 Align VecAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in LowerCall()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | SILowerSGPRSpills.cpp | 228 TRI->getSpillAlign(*RC), true); in spillCalleeSavedRegs()
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| D | SIMachineFunctionInfo.cpp | 526 TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false); in getScavengeFI()
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| D | SIFrameLowering.cpp | 76 Align Alignment = TRI->getSpillAlign(RC); in getVGPRSpillLaneOrTempRegister()
1323 TRI->getSpillAlign(*RC)); in processFunctionBeforeFrameFinalized()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARC/ |
| D | ARCFrameLowering.cpp | 443 RegInfo->getSpillAlign(*RC), false); in processFunctionBeforeFrameFinalized()
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | VirtRegMap.cpp | 97 Align Alignment = TRI->getSpillAlign(*RC); in createSpillSlot()
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| D | RegisterScavenging.cpp | 460 Align NeedAlign = TRI->getSpillAlign(RC); in spill()
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| D | PrologEpilogInserter.cpp | 526 Align Alignment = RegInfo->getSpillAlign(*RC); in assignCalleeSavedSpillSlots()
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| D | RegAllocFast.cpp | 335 Align Alignment = TRI->getSpillAlign(RC); in getStackSpaceFor()
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| /openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 291 Align getSpillAlign(const TargetRegisterClass &RC) const { in getSpillAlign() function
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| /openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/ |
| D | RISCVFrameLowering.cpp | 1117 RegInfo->getSpillAlign(*RC), false); in processFunctionBeforeFrameFinalized()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| D | SystemZFrameLowering.cpp | 1032 Align Alignment = TRI->getSpillAlign(*RC); in assignCalleeSavedSpillSlots()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 3113 Align Alignment = TRI->getSpillAlign(RC); in determineCalleeSaves()
3179 Align Alignment(RegInfo->getSpillAlign(*RC)); in assignCalleeSavedSpillSlots()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 2297 Align Alignment = TRI.getSpillAlign(RC); in addScavengingSpillSlot()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 2761 Align Alignment = TRI->getSpillAlign(RC); in determineCalleeSaves()
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