Searched refs:SrcOp2 (Results 1 – 3 of 3) sorted by relevance
| /openbsd/src/gnu/llvm/llvm/utils/TableGen/ |
| D | AsmMatcherEmitter.cpp | 1843 unsigned SrcOp2 = 0; in buildAliasResultOperands() local
1854 SrcOp2 = findAsmOperandNamed(Name, Insert.first->second); in buildAliasResultOperands()
1859 Insert.first->second = SrcOp2; in buildAliasResultOperands()
1863 SrcOp2 = (SrcOp2 == (unsigned)-1) ? SrcOp1 : SrcOp2; in buildAliasResultOperands()
1875 SrcOp2 = findAsmOperand(Name, SubIdx); in buildAliasResultOperands()
1877 ResOperand::getTiedOp((unsigned)-1, SrcOp1, SrcOp2)); in buildAliasResultOperands()
1879 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, SrcOp1, SrcOp2)); in buildAliasResultOperands()
2173 uint8_t SrcOp2 = in emitConvertFuncs() local
2178 utostr(SrcOp1) + '_' + utostr(SrcOp2); in emitConvertFuncs()
2183 ConversionRow.push_back(SrcOp2); in emitConvertFuncs()
[all …]
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1912 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx); in getShuffleComment() local
1918 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem"; in getShuffleComment()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 23527 auto SrcOp2 = Op.getOperand(1); in LowerFixedLengthConcatVectorsToSVE() local
23545 SrcOp2 = convertToScalableVector(DAG, ContainerVT, SrcOp2); in LowerFixedLengthConcatVectorsToSVE()
23547 Op = DAG.getNode(AArch64ISD::SPLICE, DL, ContainerVT, Pg, SrcOp1, SrcOp2); in LowerFixedLengthConcatVectorsToSVE()
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