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Searched refs:SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT (Results 1 – 15 of 15) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h7637 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 macro
Dgfx_7_2_sh_mask.h9170 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 macro
Dgfx_8_0_sh_mask.h10890 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 macro
Dgfx_8_1_sh_mask.h11288 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 macro
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h21557 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … macro
Dgc_9_4_3_sh_mask.h25026 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … macro
Dgc_9_1_sh_mask.h22864 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … macro
Dgc_9_2_1_sh_mask.h22831 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … macro
Dgc_9_4_2_sh_mask.h16646 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … macro
Dgc_11_5_0_sh_mask.h27604 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … macro
Dgc_11_0_0_sh_mask.h31755 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … macro
Dgc_12_0_0_sh_mask.h35732 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … macro
Dgc_11_0_3_sh_mask.h34253 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … macro
Dgc_10_1_0_sh_mask.h31502 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … macro
Dgc_10_3_0_sh_mask.h29870 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT … macro