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Searched refs:RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV5__SHIFT (Results 1 – 4 of 4) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_sh_mask.h35282 #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV5__SHIFT … macro
Dgc_11_0_0_sh_mask.h40353 #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV5__SHIFT … macro
Dgc_12_0_0_sh_mask.h39082 #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV5__SHIFT … macro
Dgc_11_0_3_sh_mask.h43391 #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV5__SHIFT … macro