Searched refs:FP0 (Results 1 – 7 of 7) sorted by relevance
| /freebsd-9-stable/contrib/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 119 if (Reg < X86::FP0 || Reg > X86::FP6) in calcLiveInMask()
121 Mask |= 1 << (Reg - X86::FP0); in calcLiveInMask()
333 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); in getFPReg()
334 return Reg - X86::FP0; in getFPReg()
345 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!"); in runOnMachineFunction()
347 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) { in runOnMachineFunction()
464 if (Reg >= X86::FP0 && Reg <= X86::FP6) { in processBasicBlock()
465 DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n"); in processBasicBlock()
466 freeStackSlotAfter(I, Reg-X86::FP0); in processBasicBlock()
992 bool KillsSrc = MI->killsRegister(X86::FP0+Reg); in handleOneArgFP()
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| D | X86RegisterInfo.td | 162 def FP0 : X86Reg<"fp0", 0>;
252 def ST7 : STRegister<"st(7)", 7, [FP0]>, DwarfRegNum<[40, 19, 18]>;
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| D | X86InstrCompiler.td | 391 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
410 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
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| /freebsd-9-stable/contrib/gdb/gdb/ |
| D | dpx2-nat.c | 42 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
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| /freebsd-9-stable/sys/dev/drm2/i915/ |
| D | i915_reg.h | 914 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) macro
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| D | intel_display.c | 5178 I915_WRITE(FP0(pipe), fp); in i9xx_update_pll_dividers()
6940 fp = I915_READ(FP0(pipe)); in intel_crtc_clock_get()
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| /freebsd-9-stable/contrib/gcc/ |
| D | FSFChangeLog.11 | 3226 (REG_ALLOC_ORDER): Move FP0 behind FP7.
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