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Searched refs:ROR (Results 1 – 25 of 45) sorted by relevance

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/freebsd-13-stable/crypto/openssl/crypto/sha/asm/
HDsha512-ppc.pl84 $ROR="rotrdi";
96 $ROR="rotrwi";
134 $ROR $a0,$e,$Sigma1[0]
135 $ROR $a1,$e,$Sigma1[1]
140 $ROR $a1,$a1,`$Sigma1[2]-$Sigma1[1]`
147 $ROR $a0,$a,$Sigma0[0]
148 $ROR $a1,$a,$Sigma0[1]
152 $ROR $a1,$a1,`$Sigma0[2]-$Sigma0[1]`
173 $ROR $a0,@X[($i+1)%16],$sigma0[0]
174 $ROR $a1,@X[($i+1)%16],$sigma0[1]
[all …]
/freebsd-13-stable/sys/crypto/openssl/arm/
HDsha1-armv4-large.S50 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
56 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
75 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
81 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
100 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
106 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
125 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
131 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
150 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
156 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
[all …]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/M68k/
HDM68kInstrShiftRotate.td16 /// ROL [~] ROR [~] ROXL [ ] ROXR [ ]
98 defm ROR : MxSROp<"ror", rotr, MxRODI_R, MxROOP_RO>;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
HDAArch64AddressingModes.h37 ROR, enumerator
58 case AArch64_AM::ROR: return "ror"; in getShiftExtendName()
79 case 3: return AArch64_AM::ROR; in getShiftType()
107 case AArch64_AM::ROR: STEnc = 3; break; in getShifterImm()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64SchedPredicates.td57 def CheckShiftROR : CheckImmOperand_s<3, "AArch64_AM::ROR">;
342 // Identify EXTR as the alias for ROR (immediate).
HDAArch64SchedNeoverseV1.td525 // Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
532 // Arithmetic, flagset, LSR/ASR/ROR shift or LSL shift > 4
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/
HDAVRISelLowering.h53 ROR, ///< Bit rotate right. enumerator
HDAVRISelLowering.cpp241 NODE(ROR); in getTargetNodeName()
365 Opc8 = AVRISD::ROR; in LowerShifts()
417 DAG.getNode(AVRISD::ROR, dl, VT, Victim, DAG.getConstant(1, dl, VT)); in LowerShifts()
428 DAG.getNode(AVRISD::ROR, dl, VT, Victim, DAG.getConstant(1, dl, VT)); in LowerShifts()
/freebsd-13-stable/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
HDARMUtils.h182 static inline uint32_t ROR(const uint32_t value, const uint32_t amount, in ROR() function
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
HDRISCVOptWInstrs.cpp254 case RISCV::ROR: in hasAllNBitUsers()
HDRISCVInstrInfoZb.td309 def ROR : ALU_rr<0b0110000, 0b101, "ror">,
504 def : PatGprGpr<shiftop<rotr>, ROR>;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
HDAArch64BaseInfo.h609 ROR, enumerator
/freebsd-13-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
HDEmulateInstructionARM.cpp1755 R[t] = ROR(data, 8*UInt(address<1:0>)); in EmulateLDRRtPCRelative()
6340 R[t] = ROR(data, 8*UInt(address<1:0>)); in EmulateLDRImmediateARM()
6445 data = ROR(data, Bits32(address, 1, 0), &success); in EmulateLDRImmediateARM()
6478 R[t] = ROR(data, 8*UInt(address<1:0>)); in EmulateLDRRegister()
6650 data = ROR(data, Bits32(address, 1, 0), &success); in EmulateLDRRegister()
8326 rotated = ROR(R[m], rotation); in EmulateSXTB()
8381 uint64_t rotated = ROR(Rm, rotation, &success); in EmulateSXTB()
8411 rotated = ROR(R[m], rotation); in EmulateSXTH()
8466 uint64_t rotated = ROR(Rm, rotation, &success); in EmulateSXTH()
8496 rotated = ROR(R[m], rotation); in EmulateUXTB()
[all …]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86InstrShiftRotate.td231 defm ROR: ShiftRotate<"ror", MRM1r, MRM1m, rotr, WriteRotateCL, WriteRotate, WriteRotateCLLd, Write…
240 defm ROR: ShiftRotate_NF<"ror", MRM1r, MRM1m, WriteRotateCL, WriteRotate, WriteRotateCLLd, WriteRot…
HDX86SchedSandyBridge.td993 "ROR(8|16|32|64)m(1|i)")>;
1031 "ROR(8|16|32|64)mCL",
HDX86ScheduleZnver4.td1585 "(V?)P(ROL|ROR)(D|Q|VD|VQ)(Z?|Z128?|Z256?)(rr|rrk|rrkz)",
1586 "(V?)P(ROL|ROR)(D|Q|VD|VQ)(Z256?)(ri|rik|rikz)",
1587 "(V?)P(ROL|ROR)(D|Q)(Z?|Z128?)(ri|rik|rikz)",
HDX86SchedSkylakeClient.td1147 "ROR(8|16|32|64)m(1|i)")>;
1230 "ROR(8|16|32|64)mCL",
HDX86SchedBroadwell.td1091 "ROR(8|16|32|64)m(1|i)")>;
1165 "ROR(8|16|32|64)mCL",
HDX86SchedHaswell.td1193 "ROR(8|16|32|64)m(1|i)")>;
1324 "ROR(8|16|32|64)mCL",
HDX86ScheduleAtom.td514 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMScheduleM7.td338 def : InstRW<[WriteALUsi], (instregex "(t|t2)(LSL|LSR|ASR|ROR)")>;
HDARMScheduleSwift.td154 // ASR,LSL,ROR,RRX
HDARMScheduleM85.td439 (instregex "(t|t2)(LSL|LSR|ASR|ROR|SBFX|UBFX)", "t2MOVsr(a|l)")>;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
HDAArch64AsmParser.cpp1495 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR || in isShifter()
1608 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR) && in isLogicalShifter()
3594 .Case("ror", AArch64_AM::ROR) in tryParseOptionalShiftExtend()
3616 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/
HDARCInstrInfo.td305 defm ROR : ArcBinaryEXT5Inst<0b000011, "ror">;

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