Searched refs:setRegAllocationHint (Results 1 – 6 of 6) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIShrinkInstructions.cpp | 365 MRI.setRegAllocationHint(Dest->getReg(), 0, SrcReg->getReg()); in shrinkScalarLogicOp()
366 MRI.setRegAllocationHint(SrcReg->getReg(), 0, Dest->getReg()); in shrinkScalarLogicOp()
667 MRI.setRegAllocationHint(Dest->getReg(), 0, Src0->getReg()); in runOnMachineFunction()
668 MRI.setRegAllocationHint(Src0->getReg(), 0, Dest->getReg()); in runOnMachineFunction()
752 MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, VCCReg); in runOnMachineFunction()
768 MRI.setRegAllocationHint(SReg, 0, VCCReg); in runOnMachineFunction()
788 MRI.setRegAllocationHint(SDst->getReg(), 0, VCCReg); in runOnMachineFunction()
796 MRI.setRegAllocationHint(Src2->getReg(), 0, VCCReg); in runOnMachineFunction()
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| D | SIInstrInfo.cpp | 7378 MRI.setRegAllocationHint(UnusedCarry, 0, RI.getVCC()); in getAddNoCarry()
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 765 void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) { in setRegAllocationHint() function
782 setRegAllocationHint(VReg, /*Type=*/0, PrefReg); in setSimpleHint()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 392 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); in updateRegAllocHint()
394 MRI->setRegAllocationHint(NewReg, in updateRegAllocHint()
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| D | MVETPAndVPTOptimisationsPass.cpp | 1017 MF->getRegInfo().setRegAllocationHint(R, ARMRI::RegLR, 0); in HintDoLoopStartReg()
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| D | ARMLoadStoreOptimizer.cpp | 2474 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2475 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
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