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Searched refs:INTSTAT (Results 1 – 18 of 18) sorted by relevance

/freebsd-12-stable/sys/dev/aic/
Daic.c482 while (!(aic_inb(aic, DMASTAT) & INTSTAT) && in aic_spiordy()
485 return !(aic_inb(aic, DMASTAT) & INTSTAT); in aic_spiordy()
879 if (dmastat & (INTSTAT|DFIFOFULL)) in aic_datain()
917 if (dmastat & INTSTAT) in aic_datain()
949 if (dmastat & (INTSTAT|DFIFOEMP)) in aic_dataout()
952 if (dmastat & INTSTAT) in aic_dataout()
985 if (dmastat & INTSTAT) { in aic_dataout()
1031 (aic_inb(aic, DMASTAT) & INTSTAT) == 0) in aic_cmd()
1191 if (!(aic_inb(aic, DMASTAT) & INTSTAT)) in aic_intr_locked()
Daic6360reg.h295 #define INTSTAT 0x20 macro
/freebsd-12-stable/sys/dev/tx/
Dif_tx.c875 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) { in epic_intr()
876 CSR_WRITE_4(sc, INTSTAT, status); in epic_intr()
1313 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT)); in epic_init_locked()
1447 status = CSR_READ_4(sc, INTSTAT) & in epic_stop_activity()
1458 status = CSR_READ_4(sc, INTSTAT); in epic_stop_activity()
1534 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) in epic_queue_last_packet()
1539 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0) in epic_queue_last_packet()
Dif_txreg.h43 #define INTSTAT 0x0004 /* Interrupt status. See below */ macro
/freebsd-12-stable/sys/dev/aic7xxx/
Daic79xx_pci.c519 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { in ahd_pci_test_register_access()
531 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { in ahd_pci_test_register_access()
840 intstat = ahd_inb(ahd, INTSTAT); in ahd_pci_intr()
Daic7xxx_osm.h186 ahc_inb(ahc, INTSTAT); in ahc_flush_device_writes()
Daic79xx_osm.h190 ahd_inb(ahd, INTSTAT); in ahd_flush_device_writes()
Daic7xxx_inline.h116 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) in ahc_unpause()
595 intstat = ahc_inb(ahc, INTSTAT); in ahc_intr()
Daic79xx_inline.h228 if ((ahd_inb(ahd, INTSTAT) & ~CMDCMPLT) == 0) in ahd_unpause()
923 intstat = ahd_inb(ahd, INTSTAT); in ahd_intr()
Daic7xxx.seq644 mvi INTSTAT,CMDCMPLT ret;
1693 mvi INTSTAT,CMDCMPLT ret;
1828 mvi INTSTAT, OUT_OF_RANGE;
1832 mvi INTSTAT, OUT_OF_RANGE;
1840 mvi INTSTAT, OUT_OF_RANGE;
1844 mvi INTSTAT, OUT_OF_RANGE;
2400 mov INTSTAT, SINDEX;
Daic7xxx_pci.c1198 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 in ahc_probe_ext_scbram()
1210 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 in ahc_probe_ext_scbram()
Daic7xxx_reg.h1518 #define INTSTAT 0x91 macro
Daic7xxx.c5208 intstat = ahc_inb(ahc, INTSTAT); in ahc_pause_and_flushwork()
5211 intstat = ahc_inb(ahc, INTSTAT); in ahc_pause_and_flushwork()
5219 ahc_inb(ahc, INTSTAT)); in ahc_pause_and_flushwork()
Daic79xx.c7169 intstat = ahd_inb(ahd, INTSTAT); in ahd_pause_and_flushwork()
7172 intstat = ahd_inb(ahd, INTSTAT); in ahd_pause_and_flushwork()
7182 ahd_inb(ahd, INTSTAT)); in ahd_pause_and_flushwork()
9037 ahd_intstat_print(ahd_inb(ahd, INTSTAT), &cur_col, 50); in ahd_dump_card_state()
Daic7xxx.reg800 register INTSTAT {
Daic79xx_reg.h2388 #define INTSTAT 0x01 macro
Daic79xx.reg102 register INTSTAT {
Daic79xx.seq286 mvi INTSTAT, CMDCMPLT;