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Searched refs:Q3 (Results 1 – 25 of 29) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/xray/
HDxray_trampoline_AArch64.S26 STP Q2, Q3, [SP, #-32]!
45 LDP Q2, Q3, [SP], #32
114 STP Q2, Q3, [SP, #-32]!
135 LDP Q2, Q3, [SP], #32
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMCallingConv.td77 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
84 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
85 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>,
86 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>,
97 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
142 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
143 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>,
145 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>,
146 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>
223 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
[all …]
HDARMCallingConv.cpp164 static const MCPhysReg QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
HDARMRegisterInfo.td160 def Q3 : ARMReg< 3, "q3", [D6, D7]>;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64CallingConvention.td104 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
106 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
108 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
111 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
113 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
146 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
148 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
150 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
153 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
155 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
[all …]
HDAArch64CallingConvention.cpp36 AArch64::Q3, AArch64::Q4, AArch64::Q5,
HDAArch64PBQPRegAlloc.cpp80 case AArch64::Q3: in isOdd()
HDAArch64SchedPredicates.td173 CheckRegOperand<0, Q3>,
HDAArch64RegisterInfo.td391 def Q3 : AArch64Reg<3, "q3", [D3], ["v3", ""]>, DwarfRegAlias<B3>;
752 def Z3 : AArch64Reg<3, "z3", [Q3, Z3_HI]>, DwarfRegNum<[99]>;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonVectorPrint.cpp76 || (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
87 if (R >= Hexagon::Q0 && R <= Hexagon::Q3) { in getStringReg()
191 } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) { in runOnMachineFunction()
HDHexagonRegisterInfo.cpp77 Q0, Q1, Q2, Q3, 0 in getCallerSavedRegs()
HDHexagonRegisterInfo.td225 def Q3 : Rq<3, "q3">, DwarfRegNum<[134]>;
323 (add Q0, Q1, Q2, Q3)> {
/freebsd-11-stable/lib/msun/src/
HDs_expm1.c126 Q3 = -7.93650757867487942473e-05, /* BF14CE19 9EAADBB7 */ variable
186 r1 = one+hxs*(Q1+hxs*(Q2+hxs*(Q3+hxs*(Q4+hxs*Q5)))); in expm1()
/freebsd-11-stable/lib/msun/bsdsrc/
HDb_tgamma.c105 #define Q3 -1.46734131782005422506287573015e-01 macro
254 q = Q0 +z*(Q1+z*(Q2+z*(Q3+z*(Q4+z*(Q5+z*(Q6+z*(Q7+z*Q8)))))));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
HDAArch64MCTargetDesc.cpp198 {codeview::RegisterId::ARM64_Q3, AArch64::Q3}, in initLLVMToCVRegMapping()
HDAArch64InstPrinter.cpp1167 case AArch64::Q2: Reg = AArch64::Q3; break; in getNextVectorRegister()
1168 case AArch64::Q3: Reg = AArch64::Q4; break; in getNextVectorRegister()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/
HDSparcDisassembler.cpp94 SP::Q3, SP::Q11, ~0U, ~0U,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
HDSparcRegisterInfo.td269 def Q3 : Rq<12, "F12", [D6, D7]>;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
HDHexagonDisassembler.cpp639 Hexagon::Q2, Hexagon::Q3}; in DecodeHvxQRRegisterClass()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
HDAArch64Disassembler.cpp305 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
629 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
/freebsd-11-stable/contrib/sendmail/contrib/
HDmail.local.linux64 M6M2[:GPH>=&+?>3Q3[Z@PR^2C2M@`VO9H4B6L(7MUV$&EIBO=F:QS96!;ZKJ
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/
HDSparcAsmParser.cpp159 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
HDARMMCCodeEmitter.cpp579 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: in getMachineOpValue()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
HDARMDisassembler.cpp1364 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1383 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
HDAArch64AsmParser.cpp2093 .Case("v3", AArch64::Q3) in MatchNeonVectorRegName()

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