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Searched refs:mmHDP_NONSURFACE_BASE (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/hdp/
HDhdp_4_0_offset.h32 #define mmHDP_NONSURFACE_BASE 0x0040 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/oss/
HDoss_1_0_d.h145 #define mmHDP_NONSURFACE_BASE 0x0B01 macro
HDoss_2_4_d.h380 #define mmHDP_NONSURFACE_BASE 0xb01 macro
HDoss_3_0_1_d.h501 #define mmHDP_NONSURFACE_BASE 0xb01 macro
HDoss_3_0_d.h596 #define mmHDP_NONSURFACE_BASE 0xb01 macro
HDoss_2_0_d.h551 #define mmHDP_NONSURFACE_BASE 0xb01 macro
/dragonfly/sys/dev/drm/amd/amdgpu/
HDgmc_v9_0.c1061 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); in gmc_v9_0_gart_enable()
HDgmc_v8_0.c489 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); in gmc_v8_0_mc_program()