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Searched refs:mmCP_ME_CNTL (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/inc/
HDpolaris10_pwrvirus.h51 { 0x15000000, mmCP_ME_CNTL },
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_d.h447 #define mmCP_ME_CNTL 0x21B6 macro
HDgfx_7_0_d.h505 #define mmCP_ME_CNTL 0x21b6 macro
HDgfx_7_2_d.h518 #define mmCP_ME_CNTL 0x21b6 macro
HDgfx_8_0_d.h571 #define mmCP_ME_CNTL 0x21b6 macro
HDgfx_8_1_d.h571 #define mmCP_ME_CNTL 0x21b6 macro
/dragonfly/sys/dev/drm/amd/amdgpu/
HDgfx_v9_0.c2320 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); in gfx_v9_0_cp_gfx_enable()
2329 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v9_0_cp_gfx_enable()
HDgfx_v8_0.c4270 u32 tmp = RREG32(mmCP_ME_CNTL); in gfx_v8_0_cp_gfx_enable()
4283 WREG32(mmCP_ME_CNTL, tmp); in gfx_v8_0_cp_gfx_enable()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h192 #define mmCP_ME_CNTL … macro
HDgc_9_2_1_offset.h186 #define mmCP_ME_CNTL … macro
HDgc_9_1_offset.h192 #define mmCP_ME_CNTL … macro