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/dragonfly/contrib/binutils-2.27/gprof/
HDbsd_callg_bl.m31 its membership in a cycle, if any.
58 parent's membership in a cycle, if any.
84 membership in a cycle, if any.
92 children) in the same cycle as the function. If
93 the function (or child) is a member of a cycle,
96 cycle as a whole.
103 cycle listings:
104 the cycle as a whole is listed with the same
106 the members of the cycle, and their contributions
107 to the time and call counts of the cycle.
HDfsf_callg_bl.m32 cycle, the cycle number is printed between the
51 member of a cycle, the cycle number is printed between
73 member of a cycle, the cycle number is printed
77 entry for the cycle-as-a-whole. This entry shows who called the
78 cycle (as parents) and the members of the cycle (as children.)
80 were internal to the cycle, and the calls entry for each member shows,
82 the cycle.
HDgprof.texi150 Cycles are discovered, and calls into a cycle are made to share the time
151 of the cycle.
1066 0.00 0.00 12/34 strncmp <cycle 1> [40]
1072 [4] 59.8 0.01 0.02 8+472 <cycle 2 as a whole> [4]
1073 0.01 0.02 244+260 offtime <cycle 2> [7]
1074 0.00 0.00 236+1 tzset <cycle 2> [26]
1165 If the function is part of a cycle of recursion, the cycle number is
1169 cycle number one, and has index number twelve, its primary line would
1173 gnurr <cycle 1> [12]
1224 If the caller is part of a recursion cycle, the cycle number is
[all …]
HDgprof.info862 0.00 0.00 12/34 strncmp <cycle 1> [40]
868 [4] 59.8 0.01 0.02 8+472 <cycle 2 as a whole> [4]
869 0.01 0.02 244+260 offtime <cycle 2> [7]
870 0.00 0.00 236+1 tzset <cycle 2> [26]
960 If the function is part of a cycle of recursion, the cycle number
963 example, if function `gnurr' is part of cycle number one, and has
966 gnurr <cycle 1> [12]
1015 If the caller is part of a recursion cycle, the cycle number is
1067 If the caller is part of a recursion cycle, the cycle number is
1077 in the call graph. A cycle exists if a function calls another function
[all …]
/dragonfly/contrib/binutils-2.34/gprof/
HDbsd_callg_bl.m31 its membership in a cycle, if any.
58 parent's membership in a cycle, if any.
84 membership in a cycle, if any.
92 children) in the same cycle as the function. If
93 the function (or child) is a member of a cycle,
96 cycle as a whole.
103 cycle listings:
104 the cycle as a whole is listed with the same
106 the members of the cycle, and their contributions
107 to the time and call counts of the cycle.
HDfsf_callg_bl.m32 cycle, the cycle number is printed between the
51 member of a cycle, the cycle number is printed between
73 member of a cycle, the cycle number is printed
77 entry for the cycle-as-a-whole. This entry shows who called the
78 cycle (as parents) and the members of the cycle (as children.)
80 were internal to the cycle, and the calls entry for each member shows,
82 the cycle.
/dragonfly/lib/libthread_xu/thread/
HDthr_barrier.c82 int64_t cycle; in _pthread_barrier_wait() local
99 cycle = bar->b_cycle; in _pthread_barrier_wait()
102 _thr_umtx_wait(&bar->b_cycle, cycle, NULL, 0); in _pthread_barrier_wait()
104 } while (cycle == bar->b_cycle); in _pthread_barrier_wait()
HDthr_sig.c84 umtx_t cycle; in _thr_suspend_check() local
100 curthread->cycle++; in _thr_suspend_check()
101 cycle = curthread->cycle; in _thr_suspend_check()
104 _thr_umtx_wake(&curthread->cycle, 0); in _thr_suspend_check()
114 _thr_umtx_wait(&curthread->cycle, cycle, NULL, 0); in _thr_suspend_check()
HDthr_resume_np.c86 thread->cycle++; in resume_common()
87 _thr_umtx_wake(&thread->cycle, 1); in resume_common()
HDthr_suspend_np.c123 tmp = thread->cycle; in suspend_common()
127 _thr_umtx_wait(&thread->cycle, tmp, NULL, 0); in suspend_common()
HDthr_create.c181 new_thread->cycle++; in _pthread_create()
182 _thr_umtx_wake(&new_thread->cycle, 0); in _pthread_create()
/dragonfly/contrib/gcc-8.0/gcc/
HDmcf.c785 int *pi, gcov_type *d, int *cycle) in cancel_negative_cycle() argument
808 cycle[i] = -1; in cancel_negative_cycle()
858 cycle[0] = pfedge->dest; in cancel_negative_cycle()
864 cycle[i] = j; in cancel_negative_cycle()
867 if (cycle[k] == j) in cancel_negative_cycle()
880 gcc_assert (cycle[cycle_start] == cycle[cycle_end]); in cancel_negative_cycle()
889 pfedge = find_fixup_edge (fixup_graph, cycle[k + 1], cycle[k]); in cancel_negative_cycle()
893 fprintf (dump_file, "%d ", cycle[k]); in cancel_negative_cycle()
898 fprintf (dump_file, "%d", cycle[k]); in cancel_negative_cycle()
909 pfedge = find_fixup_edge (fixup_graph, cycle[k + 1], cycle[k]); in cancel_negative_cycle()
[all …]
HDmodulo-sched.c130 int cycle; member
461 update_node_sched_params (int u, int ii, int cycle, int min_cycle) in update_node_sched_params() argument
466 SCHED_TIME (u) = cycle; in update_node_sched_params()
467 SCHED_ROW (u) = SMODULO (cycle, ii); in update_node_sched_params()
865 crr_insn->cycle = normalized_time; in reset_sched_times()
2109 int u, int cycle, sbitmap sched_nodes, in try_scheduling_node_in_cycle() argument
2117 psi = ps_add_node_check_conflicts (ps, u, cycle, must_precede, must_follow); in try_scheduling_node_in_cycle()
2120 SCHED_TIME (u) = cycle; in try_scheduling_node_in_cycle()
2125 fprintf (dump_file, "Scheduled w/o split in %d\n", cycle); in try_scheduling_node_in_cycle()
2299 crr_insn->cycle = new_time; in ps_insert_empty_row()
[all …]
/dragonfly/contrib/gcc-4.7/gcc/
HDmcf.c789 int *pi, gcov_type *d, int *cycle) in cancel_negative_cycle() argument
812 cycle[i] = -1; in cancel_negative_cycle()
862 cycle[0] = pfedge->dest; in cancel_negative_cycle()
868 cycle[i] = j; in cancel_negative_cycle()
871 if (cycle[k] == j) in cancel_negative_cycle()
884 gcc_assert (cycle[cycle_start] == cycle[cycle_end]); in cancel_negative_cycle()
893 pfedge = find_fixup_edge (fixup_graph, cycle[k + 1], cycle[k]); in cancel_negative_cycle()
897 fprintf (dump_file, "%d ", cycle[k]); in cancel_negative_cycle()
902 fprintf (dump_file, "%d", cycle[k]); in cancel_negative_cycle()
913 pfedge = find_fixup_edge (fixup_graph, cycle[k + 1], cycle[k]); in cancel_negative_cycle()
[all …]
HDgcov.c102 unsigned int cycle : 1; member
157 } cycle; /* Used in all-blocks mode, after blocks are linked onto member
1944 block->u.cycle.arc = NULL; in add_line_counts()
1945 block->u.cycle.ident = ~0U; in add_line_counts()
2028 block->u.cycle.ident = ix; in accumulate_line_counts()
2039 if (arc->src->u.cycle.ident != ix) in accumulate_line_counts()
2078 arc->cycle in accumulate_line_counts()
2080 || dst->u.cycle.ident != ix in accumulate_line_counts()
2082 || dst->u.cycle.arc) in accumulate_line_counts()
2096 for (dst = head; (probe_arc = dst->u.cycle.arc); in accumulate_line_counts()
[all …]
HDmodulo-sched.c134 int cycle; member
475 update_node_sched_params (int u, int ii, int cycle, int min_cycle) in update_node_sched_params() argument
480 SCHED_TIME (u) = cycle; in update_node_sched_params()
481 SCHED_ROW (u) = SMODULO (cycle, ii); in update_node_sched_params()
876 crr_insn->cycle = normalized_time; in reset_sched_times()
2125 int u, int cycle, sbitmap sched_nodes, in try_scheduling_node_in_cycle() argument
2133 psi = ps_add_node_check_conflicts (ps, u, cycle, must_precede, must_follow); in try_scheduling_node_in_cycle()
2136 SCHED_TIME (u) = cycle; in try_scheduling_node_in_cycle()
2141 fprintf (dump_file, "Scheduled w/o split in %d\n", cycle); in try_scheduling_node_in_cycle()
2320 crr_insn->cycle = new_time; in ps_insert_empty_row()
[all …]
/dragonfly/usr.sbin/fwcontrol/
HDfwdv.c254 int systype=-1, pad_acc, cycle_acc=0, cycle=0, f_frac; in dvsend() local
347 cycle = 1; in dvsend()
348 cycle_acc = frame_cycle[systype].d * cycle; in dvsend()
365 ciph->fdf.dv.cyc = htons(cycle << 12 | f_frac); in dvsend()
382 cycle ++; in dvsend()
390 cycle ++; in dvsend()
/dragonfly/contrib/gcc-8.0/gcc/config/i386/
HDpentium.md84 ;; We add dummy "port" pipes allocated only first cycle of
93 ;; instructions. We model only first cycle of FP pipeline, as it is
103 ;; last cycle of first instruction, when data are bypassed.
153 ;; Moves usually have one cycle penalty, but there are exceptions.
179 ;; Push and pop instructions have 1 cycle latency and special
234 ;; load/execute 2 cycles and execute only one cycle.
HDppro.md76 ;; decoders in one cycle.
78 ;; but still in only one cycle.
83 ;; in each cycle, to decode as many instructions per cycle as possible.
97 ;; The out-of-order core has five pipelines. During each cycle, the core
99 ;; so the maximum number of dispatched uops per cycle is 5. In practicer,
100 ;; 3 uops per cycle is more realistic.
202 ;; branches cost only one fetch cycle. Mispredicted branches are very
293 ;; has throughput "1/cycle (align with FADD)". What do they
442 ;; throughput of 1/cycle.
HDatom.md52 ;;; Most of simple instructions have 1 cycle latency. Some of them
58 ;;; Some insn issues in port 0 with 3 cycle latency and 1 cycle tput
399 ;; pop r64 is 1 cycle. UCODE if segreg, ignored
626 ;; Except dppd/dpps, 4 cycle if mulss
763 ;; There will be 0 cycle stall from cmp/test to jcc
765 ;; There will be 1 cycle stall from flag producer to cmov and adc/sbb
778 ;; lea to shift source stall is 1 cycle
783 ;; non-lea to shift count stall is 1 cycle
/dragonfly/contrib/gcc-4.7/gcc/config/i386/
HDpentium.md84 ;; We add dummy "port" pipes allocated only first cycle of
93 ;; instructions. We model only first cycle of FP pipeline, as it is
103 ;; last cycle of first instruction, when data are bypassed.
153 ;; Moves usually have one cycle penalty, but there are exceptions.
179 ;; Push and pop instructions have 1 cycle latency and special
234 ;; load/execute 2 cycles and execute only one cycle.
HDppro.md76 ;; decoders in one cycle.
78 ;; but still in only one cycle.
83 ;; in each cycle, to decode as many instructions per cycle as possible.
97 ;; The out-of-order core has five pipelines. During each cycle, the core
99 ;; so the maximum number of dispatched uops per cycle is 5. In practicer,
100 ;; 3 uops per cycle is more realistic.
202 ;; branches cost only one fetch cycle. Mispredicted branches are very
293 ;; has throughput "1/cycle (align with FADD)". What do they
442 ;; throughput of 1/cycle.
HDatom.md52 ;;; Most of simple instructions have 1 cycle latency. Some of them
58 ;;; Some insn issues in port 0 with 3 cycle latency and 1 cycle tput
399 ;; pop r64 is 1 cycle. UCODE if segreg, ignored
628 ;; Except dppd/dpps, 4 cycle if mulss
765 ;; There will be 0 cycle stall from cmp/test to jcc
767 ;; There will be 1 cycle stall from flag producer to cmov and adc/sbb
780 ;; lea to shift source stall is 1 cycle
785 ;; non-lea to shift count stall is 1 cycle
/dragonfly/usr.bin/dsynth/
HDprogress.js200 function cycle () { function
217 cycle();
226 cycle();
/dragonfly/sys/dev/sound/pcm/
HDbuffer.c692 unsigned int cycle; in sndbuf_feed() local
697 cycle = 0; in sndbuf_feed()
715 cycle++; in sndbuf_feed()
720 if (cycle > snd_feeder_maxcycle) in sndbuf_feed()
721 snd_feeder_maxcycle = cycle; in sndbuf_feed()

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