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Searched refs:ENABLE_INTR (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDcz_ih.c63 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in cz_ih_enable_interrupts()
83 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in cz_ih_disable_interrupts()
HDiceland_ih.c63 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in iceland_ih_enable_interrupts()
83 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in iceland_ih_disable_interrupts()
HDtonga_ih.c63 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in tonga_ih_enable_interrupts()
80 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in tonga_ih_disable_interrupts()
HDvega10_ih.c50 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in vega10_ih_enable_interrupts()
67 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in vega10_ih_disable_interrupts()
/dragonfly/sys/dev/drm/radeon/
HDsid.h667 # define ENABLE_INTR (1 << 0) macro
HDcikd.h817 # define ENABLE_INTR (1 << 0) macro
HDevergreend.h1236 # define ENABLE_INTR (1 << 0) macro
HDr600d.h675 # define ENABLE_INTR (1 << 0) macro
HDr600.c3609 ih_cntl |= ENABLE_INTR; in r600_enable_interrupts()
3622 ih_cntl &= ~ENABLE_INTR; in r600_disable_interrupts()
HDsi.c5911 ih_cntl |= ENABLE_INTR; in si_enable_interrupts()
5924 ih_cntl &= ~ENABLE_INTR; in si_disable_interrupts()
HDcik.c6865 ih_cntl |= ENABLE_INTR; in cik_enable_interrupts()
6885 ih_cntl &= ~ENABLE_INTR; in cik_disable_interrupts()