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Searched refs:D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_sh_mask.h2534 #define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x00000008 macro
HDdce_8_0_sh_mask.h11046 #define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 macro
HDdce_10_0_sh_mask.h11430 #define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 macro
HDdce_11_0_sh_mask.h11242 #define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 macro
HDdce_11_2_sh_mask.h12496 #define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 macro
HDdce_12_0_sh_mask.h2281 #define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
HDdcn_1_0_sh_mask.h1727 #define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT … macro