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Searched refs:CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_2_sh_mask.h1488 #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 macro
HDgfx_8_1_sh_mask.h2440 #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 macro
HDgfx_8_0_sh_mask.h1918 #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h11141 #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT … macro
HDgc_9_2_1_sh_mask.h12531 #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT … macro