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Searched refs:CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDgfx_v9_0.c3581 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v9_0_update_medium_grain_clock_gating()
3610 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { in gfx_v9_0_update_medium_grain_clock_gating()
3611 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v9_0_update_medium_grain_clock_gating()
3837 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) in gfx_v9_0_get_clockgating_state()
HDgfx_v8_0.c5769 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) in gfx_v8_0_get_clockgating_state()
5962 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { in gfx_v8_0_update_medium_grain_clock_gating()
5963 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v8_0_update_medium_grain_clock_gating()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h2598 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L macro
HDgfx_7_2_sh_mask.h1435 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1 macro
HDgfx_8_1_sh_mask.h2401 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1 macro
HDgfx_8_0_sh_mask.h1879 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h11088 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK … macro
HDgc_9_2_1_sh_mask.h12492 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK … macro