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Searched refs:subtarget (Results 1 – 25 of 34) sorted by relevance

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/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetSchedule.td27 // each subtarget, define WriteRes and ReadAdvance to associate
31 // subtarget, define ItinRW entries to map ItineraryClass to
33 // be subtarget specific and can be directly associated with resources
36 // C. In the subtarget, map SchedReadWrite types to specific
39 // subtarget can directly associate resources with SchedReadWrite
42 // D. In either the target or subtarget, define SchedWriteVariant or
95 // and may actually be generated for that subtarget must clear this
249 // defined by the subtarget, and maps the SchedWrite to processor
253 // be used instead to define subtarget specific SchedWrites and map
255 // itinerary classes to the subtarget's SchedWrites.
[all …]
HDTargetCallingConv.td94 /// is used - these may depend on the target or subtarget.
HDTarget.td485 /// AssemblerCondString - Name of the subtarget feature being tested used
/NextBSD/contrib/gcc/
HDexpmed.c1770 rtx subtarget = (target != 0 && REG_P (target) ? target : 0); in extract_fixed_bit_field() local
1771 if (tmode != mode) subtarget = 0; in extract_fixed_bit_field()
1772 op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1); in extract_fixed_bit_field()
1810 rtx subtarget = (target != 0 && REG_P (target) ? target : 0); in extract_fixed_bit_field() local
1811 op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1); in extract_fixed_bit_field()
2264 rtx subtarget = target == shifted ? 0 : target; in expand_shift() local
2282 mode, shifted, other_amount, subtarget, 1); in expand_shift()
5109 rtx subtarget; in emit_store_flag() local
5214 subtarget = target; in emit_store_flag()
5226 subtarget = 0; in emit_store_flag()
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HDoptabs.c4055 rtx tem, subtarget, comparison, insn; in emit_conditional_move() local
4102 subtarget = target; in emit_conditional_move()
4107 (subtarget, insn_data[icode].operand[0].mode)) in emit_conditional_move()
4108 subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); in emit_conditional_move()
4131 insn = GEN_FCN (icode) (subtarget, comparison, op2, op3); in emit_conditional_move()
4139 if (subtarget != target) in emit_conditional_move()
4140 convert_move (target, subtarget, 0); in emit_conditional_move()
4183 rtx tem, subtarget, comparison, insn; in emit_conditional_add() local
4234 subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); in emit_conditional_add()
4236 subtarget = target; in emit_conditional_add()
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HDexpr.c5969 rtx subtarget = get_subtarget (target); in force_operand() local
5993 if (!subtarget) in force_operand()
5994 subtarget = gen_reg_rtx (GET_MODE (value)); in force_operand()
5995 emit_move_insn (subtarget, value); in force_operand()
5996 return subtarget; in force_operand()
6002 if (!CONSTANT_P (op2) && !(REG_P (op2) && op2 != subtarget)) in force_operand()
6003 subtarget = 0; in force_operand()
6024 subtarget, 0, OPTAB_LIB_WIDEN); in force_operand()
6031 op1 = force_operand (XEXP (value, 0), subtarget); in force_operand()
6497 rtx result, subtarget; in expand_expr_addr_expr_1() local
[all …]
HDbuiltins.c1774 expand_builtin_mathfn (tree exp, rtx target, rtx subtarget) in expand_builtin_mathfn() argument
1865 op0 = expand_expr (arg, subtarget, VOIDmode, 0); in expand_builtin_mathfn()
1945 expand_builtin_mathfn_2 (tree exp, rtx target, rtx subtarget) in expand_builtin_mathfn_2() argument
2020 op0 = expand_expr (arg0, subtarget, VOIDmode, EXPAND_NORMAL); in expand_builtin_mathfn_2()
2058 expand_builtin_mathfn_3 (tree exp, rtx target, rtx subtarget) in expand_builtin_mathfn_3() argument
2114 op0 = expand_expr (arg, subtarget, VOIDmode, 0); in expand_builtin_mathfn_3()
2218 expand_builtin_int_roundingfn (tree exp, rtx target, rtx subtarget) in expand_builtin_int_roundingfn() argument
2271 op0 = expand_expr (arg, subtarget, VOIDmode, 0); in expand_builtin_int_roundingfn()
2521 expand_builtin_pow (tree exp, rtx target, rtx subtarget) in expand_builtin_pow() argument
2553 rtx op = expand_expr (arg0, subtarget, VOIDmode, 0); in expand_builtin_pow()
[all …]
HDtarget.h440 rtx (* expand_builtin) (tree exp, rtx target, rtx subtarget,
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMSchedule.td12 // Here we define the subtarget independent read/write per-operand resources.
13 // The subtarget schedule definitions will then map these to the subtarget's
41 // Next, the subtarget td file assigns resources to the abstract resources
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86CallingConv.td15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
307 // subtarget.
369 // subtarget.
525 // Long doubles get slots whose size depends on the subtarget.
HDX86InstrFragmentsSIMD.td570 // be naturally aligned on some targets but not on others. If the subtarget
/NextBSD/contrib/binutils/
HDMakefile.tpl1451 (dep-subtarget var-name)
1462 ;; dep-subtarget extracts everything up to the first dash in the given
1464 (define dep-subtarget (lambda (var-name)
1495 (if (or (= (dep-subtarget "on") "install-")
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDR600InstrFormats.td180 XXX: R600 subtarget uses a slightly different encoding than the other
HDSIInstrInfo.td577 class SIMCInstr <string pseudo, int subtarget> {
579 int Subtarget = subtarget;
/NextBSD/contrib/gcc/config/ia64/
HDia64.md4569 rtx subtarget = gen_reg_rtx (DImode);
4571 emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]),
4576 emit_insn (gen_extendsidi2 (subtarget, operands[1]));
4578 emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift));
4580 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
4590 rtx subtarget = gen_reg_rtx (DImode);
4592 emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]),
4597 emit_insn (gen_zero_extendsidi2 (subtarget, operands[1]));
4599 emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift));
4601 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
HDia64.c1109 rtx subtarget = no_new_pseudos ? op0 : gen_reg_rtx (mode); in ia64_expand_move() local
1111 emit_insn (gen_rtx_SET (VOIDmode, subtarget, op1)); in ia64_expand_move()
1113 op1 = expand_simple_binop (mode, PLUS, subtarget, in ia64_expand_move()
9134 ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, in ia64_expand_builtin()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCCallingConv.td15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsCallingConv.td12 /// CCIfSubtarget - Match if the current subtarget has a feature F.
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonInstrFormats.td150 // If an instruction is valid on a subtarget, set the corresponding
/NextBSD/contrib/llvm/tools/clang/include/clang/Basic/
HDAttrDocs.td717 The current set of options correspond to the existing "subtarget features" for
722 Example "subtarget features" from the x86 backend include: "mmx", "sse", "sse4.2",
743 allocation requirements or ABI constraints of the subtarget. For
747 subtarget supports will truncate to the maximum allowed. The backend
/NextBSD/contrib/gcc/config/arm/
HDarm.md1880 rtx target, subtarget;
1883 /* Avoid using a subreg as a subtarget, and avoid writing a paradoxical
1887 subtarget = gen_reg_rtx (SImode);
1893 subtarget = target;
1910 emit_insn (gen_iorsi3 (subtarget, op1,
1929 emit_insn (gen_rotlsi3 (subtarget, op1, operands[1]));
1943 emit_insn (gen_iorsi3 (subtarget, op1, op0));
1988 emit_insn (gen_iorsi3 (subtarget, op1, op2));
1991 if (subtarget != target)
1996 emit_move_insn (target, subtarget);
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/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64SchedA57.td119 // subtarget-defined types. As the modeled is refined, this will override most
/NextBSD/contrib/gcc/config/sparc/
HDsparc.c7972 rtx subtarget ATTRIBUTE_UNUSED, in sparc_expand_builtin()
/NextBSD/contrib/gcc/config/mips/
HDmips.c10349 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, in mips_expand_builtin()
/NextBSD/contrib/gcc/config/s390/
HDs390.c8206 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, in s390_expand_builtin()

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