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Searched refs:intrs (Results 1 – 12 of 12) sorted by relevance

/NextBSD/sys/sparc64/isa/
HDisa.c146 ofw_isa_intr_t *intrs, rintr; in isa_setup_children() local
238 nintr = OF_getprop_alloc(node, "interrupts", sizeof(*intrs), in isa_setup_children()
239 (void **)&intrs); in isa_setup_children()
241 if (intrs[i] > 7) in isa_setup_children()
244 &isa_iinfo, intrs[i]); in isa_setup_children()
248 intrs[i], (unsigned long)node, name); in isa_setup_children()
253 if (intrs != NULL) in isa_setup_children()
254 free(intrs, M_OFWPROP); in isa_setup_children()
/NextBSD/sys/x86/iommu/
HDintel_drv.c231 dmd = &unit->intrs[idx]; in dmar_release_intr()
279 dmd = &unit->intrs[idx]; in dmar_alloc_irq()
347 dmd = &unit->intrs[i]; in dmar_remap_intr()
428 unit->intrs[i].irq = -1; in dmar_attach()
430 unit->intrs[DMAR_INTR_FAULT].name = "fault"; in dmar_attach()
431 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID; in dmar_attach()
432 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr; in dmar_attach()
433 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG; in dmar_attach()
434 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG; in dmar_attach()
435 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG; in dmar_attach()
[all …]
HDintel_dmar.h183 struct dmar_msi_data intrs[DMAR_INTR_TOTAL]; member
/NextBSD/sys/arm/samsung/exynos/
HDexynos5_combiner.c273 int intrs; in combiner_intr() local
281 intrs = READ4(sc, CIPSR); in combiner_intr()
283 if (intrs & (1 << grp)) { in combiner_intr()
/NextBSD/sys/sparc64/ebus/
HDebus.c649 ofw_isa_intr_t intr, *intrs; in ebus_setup_dinfo() local
675 nintr = OF_getprop_alloc(node, "interrupts", sizeof(*intrs), in ebus_setup_dinfo()
676 (void **)&intrs); in ebus_setup_dinfo()
683 intrs[i]); in ebus_setup_dinfo()
685 intr = intrs[i]; in ebus_setup_dinfo()
698 edi->edi_obdinfo.obd_name, intrs[i]); in ebus_setup_dinfo()
704 free(intrs, M_OFWPROP); in ebus_setup_dinfo()
/NextBSD/sys/dev/oce/
HDoce_if.c721 POCE_INTR_INFO ii = &sc->intrs[vector]; in oce_alloc_intr()
773 if (sc->intrs[i].tag != NULL) in oce_intr_free()
774 bus_teardown_intr(sc->dev, sc->intrs[i].intr_res, in oce_intr_free()
775 sc->intrs[i].tag); in oce_intr_free()
776 if (sc->intrs[i].tq != NULL) in oce_intr_free()
777 taskqueue_free(sc->intrs[i].tq); in oce_intr_free()
779 if (sc->intrs[i].intr_res != NULL) in oce_intr_free()
781 sc->intrs[i].irq_rr, in oce_intr_free()
782 sc->intrs[i].intr_res); in oce_intr_free()
783 sc->intrs[i].tag = NULL; in oce_intr_free()
[all …]
HDoce_queue.c607 sc->intrs[sc->neqs++].eq = eq; in oce_eq_create()
HDoce_if.h815 OCE_INTR_INFO intrs[OCE_MAX_EQ]; member
/NextBSD/sys/dev/ste/
HDif_ste.c508 uint16_t intrs, status; in ste_intr() local
527 intrs = STE_INTRS; in ste_intr()
528 if (status == 0xFFFF || (status & intrs) == 0) in ste_intr()
533 intrs &= ~STE_IMR_RX_DMADONE; in ste_intr()
554 intrs &= ~STE_IMR_RX_DMADONE; in ste_intr()
557 intrs |= STE_IMR_RX_DMADONE; in ste_intr()
579 CSR_WRITE_2(sc, STE_IMR, intrs); in ste_intr()
/NextBSD/sys/dev/bwi/
HDbwimac.c380 uint32_t intrs; in bwi_mac_init() local
383 intrs = BWI_TXRX_RX_INTRS; in bwi_mac_init()
385 intrs = BWI_TXRX_TX_INTRS; in bwi_mac_init()
386 CSR_WRITE_4(sc, BWI_TXRX_INTR_MASK(i), intrs); in bwi_mac_init()
/NextBSD/sys/dev/re/
HDif_re.c2636 uint16_t intrs, status; in re_intr_msi() local
2655 intrs = RL_INTRS_CPLUS; in re_intr_msi()
2659 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | in re_intr_msi()
2674 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | in re_intr_msi()
2678 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | in re_intr_msi()
2707 CSR_WRITE_2(sc, RL_IMR, intrs); in re_intr_msi()
/NextBSD/sys/dev/ti/
HDif_ti.c1952 uint32_t intrs; in ti_setmulti() local
1966 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); in ti_setmulti()
1996 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); in ti_setmulti()