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Searched refs:getNode (Results 1 – 25 of 123) sorted by relevance

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/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDDAGCombiner.cpp528 AddToWorklist(Op.getNode()); in deleteAndRecombine()
623 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
628 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
642 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
652 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
658 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
665 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
669 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
691 !TLI.isConstTrueVal(N.getOperand(2).getNode()) || in isSetCCEquivalent()
692 !TLI.isConstFalseVal(N.getOperand(3).getNode())) in isSetCCEquivalent()
[all …]
HDLegalizeVectorOps.cpp179 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i) in TranslateLegalizeResults()
190 SDNode* Node = Op.getNode(); in LegalizeOp()
197 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0); in LegalizeOp()
201 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode()); in LegalizeOp()
230 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode()); in LegalizeOp()
352 if (Tmp1.getNode()) { in LegalizeOp()
394 assert(Op.getNode()->getNumValues() == 1 && in Promote()
407 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j)); in Promote()
409 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j)); in Promote()
414 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands); in Promote()
[all …]
HDLegalizeDAG.cpp183 UpdatedNodes->insert(New.getNode()); in ReplaceNode()
184 ReplacedNode(Old.getNode()); in ReplaceNode()
196 UpdatedNodes->insert(New[i].getNode()); in ReplaceNode()
311 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); in ExpandUnalignedStore()
353 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, in ExpandUnalignedStore()
355 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); in ExpandUnalignedStore()
377 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); in ExpandUnalignedStore()
394 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in ExpandUnalignedStore()
403 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, in ExpandUnalignedStore()
413 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); in ExpandUnalignedStore()
[all …]
HDTargetLowering.cpp210 SDValue Tmp = DAG.getNode( in softenSetCCOperands()
216 NewLHS = DAG.getNode( in softenSetCCOperands()
220 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS); in softenSetCCOperands()
306 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), in ShrinkDemandedConstant()
331 assert(Op.getNode()->getNumValues() == 1 && in ShrinkDemandedOp()
340 if (!Op.getNode()->hasOneUse()) in ShrinkDemandedOp()
355 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, in ShrinkDemandedOp()
356 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
357 Op.getNode()->getOperand(0)), in ShrinkDemandedOp()
358 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
[all …]
HDLegalizeIntegerTypes.cpp152 if (Res.getNode()) in PromoteIntegerResult()
165 return DAG.getNode(ISD::AssertSext, SDLoc(N), in PromoteIntRes_AssertSext()
172 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
253 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST()
257 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
262 SDValue Trunc = DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp); in PromoteIntRes_BITCAST()
263 return DAG.getNode(ISD::AssertZext, dl, NOutVT, Trunc, in PromoteIntRes_BITCAST()
274 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
288 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
292 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
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HDLegalizeTypesGeneric.cpp59 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
60 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
70 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
71 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
78 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
79 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
84 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
85 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
95 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
96 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
[all …]
HDLegalizeVectorTypes.cpp134 if (R.getNode()) in ScalarizeVectorResult()
141 return DAG.getNode(N->getOpcode(), SDLoc(N), in ScalarizeVecRes_BinOp()
149 return DAG.getNode(N->getOpcode(), SDLoc(N), in ScalarizeVecRes_TernaryOp()
161 return DAG.getNode(ISD::BITCAST, SDLoc(N), in ScalarizeVecRes_BITCAST()
171 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp); in ScalarizeVecRes_BUILD_VECTOR()
187 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in ScalarizeVecRes_EXTRACT_SUBVECTOR()
195 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecRes_FP_ROUND()
201 return DAG.getNode(ISD::FPOWI, SDLoc(N), in ScalarizeVecRes_FPOWI()
212 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op); in ScalarizeVecRes_INSERT_VECTOR_ELT()
254 Op = DAG.getNode( in ScalarizeVecRes_UnaryOp()
[all …]
HDResourcePriorityQueue.cpp78 const SDNode *ScegN = PredSU->getNode(); in numberRCValPredInSU()
116 const SDNode *ScegN = SuccSU->getNode(); in numberRCValSuccInSU()
134 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU()
247 if (!SU || !SU->getNode()) in isResourceAvailable()
252 if (SU->getNode()->getGluedNode()) in isResourceAvailable()
257 if (SU->getNode()->isMachineOpcode()) in isResourceAvailable()
258 switch (SU->getNode()->getMachineOpcode()) { in isResourceAvailable()
261 SU->getNode()->getMachineOpcode()))) in isResourceAvailable()
292 if (!isResourceAvailable(SU) || SU->getNode()->getGluedNode()) { in reserveResources()
297 if (SU->getNode() && SU->getNode()->isMachineOpcode()) { in reserveResources()
[all …]
HDSelectionDAGBuilder.cpp145 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
146 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
152 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); in getCopyFromParts()
166 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); in getCopyFromParts()
168 DAG.getNode(ISD::SHL, DL, TotalVT, Hi, in getCopyFromParts()
171 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); in getCopyFromParts()
172 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); in getCopyFromParts()
179 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); in getCopyFromParts()
180 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); in getCopyFromParts()
183 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); in getCopyFromParts()
[all …]
HDLegalizeTypes.cpp104 assert(NewVal.getNode()->getNodeId() != NewNode && in PerformExpensiveChecks()
277 if (IgnoreNodeResults(N->getOperand(i).getNode())) in run()
426 if (!IgnoreNodeResults(I->getOperand(i).getNode()) && in run()
486 if (Op.getNode()->getNodeId() == Processed) in AnalyzeNewNode()
532 Val.setNode(AnalyzeNewNode(Val.getNode())); in AnalyzeNewValue()
533 if (Val.getNode()->getNodeId() == Processed) in AnalyzeNewValue()
568 assert(I->first.getNode() != N); in ExpungeNode()
574 assert(I->first.getNode() != N); in ExpungeNode()
580 assert(I->first.getNode() != N); in ExpungeNode()
586 assert(I->first.getNode() != N); in ExpungeNode()
[all …]
HDLegalizeFloatTypes.cpp110 if (R.getNode()) in SoftenFloatResult()
126 return DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), in SoftenFloatRes_BUILD_PAIR()
141 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in SoftenFloatRes_EXTRACT_VECTOR_ELT()
155 return DAG.getNode(ISD::AND, SDLoc(N), NVT, Op, Mask); in SoftenFloatRes_FABS()
221 SDValue SignBit = DAG.getNode( in SoftenFloatRes_FCOPYSIGN()
225 SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit); in SoftenFloatRes_FCOPYSIGN()
231 DAG.getNode(ISD::SRL, dl, RVT, SignBit, in SoftenFloatRes_FCOPYSIGN()
235 SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
237 SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
239 DAG.getNode(ISD::SHL, dl, LVT, SignBit, in SoftenFloatRes_FCOPYSIGN()
[all …]
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp594 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); in LowerReturn()
624 Op.getNode()->dump(); in LowerOperation()
663 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode(); in ReplaceNodeResults()
676 if (Lowered.getNode()) in ReplaceNodeResults()
728 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset); in LowerConstantInitializer()
734 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in LowerConstantInitializer()
752 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset); in LowerConstantInitializer()
758 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in LowerConstantInitializer()
871 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args); in LowerCONCAT_VECTORS()
883 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args); in LowerEXTRACT_SUBVECTOR()
[all …]
HDR600ISelLowering.cpp595 assert((!Result.getNode() || in LowerOperation()
596 Result.getNode()->getNumValues() == 2) && in LowerOperation()
626 return DAG.getNode(AMDGPUISD::EXPORT, DL, Op.getValueType(), Args); in LowerOperation()
701 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32, in LowerOperation()
775 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); in LowerOperation()
779 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
781 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
783 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
785 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
787 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
[all …]
HDSIISelLowering.cpp451 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr, in LowerParameter()
474 DAG.getNode(ISD::FP16_TO_FP, SL, VT, Load), in LowerParameter()
627 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg, in LowerFormalArguments()
674 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs)); in LowerFormalArguments()
690 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in LowerFormalArguments()
792 assert((!Result.getNode() || in LowerOperation()
793 Result.getNode()->getNumValues() == 2) && in LowerOperation()
818 SDNode *Parent = Value.getNode(); in findUser()
854 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, TFI, in LowerFrameIndex()
865 SDNode *Intr = BRCOND.getOperand(1).getNode(); in LowerBRCOND()
[all …]
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp1399 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1402 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerCallResult()
1403 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1416 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1417 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1431 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); in LowerCallResult()
1450 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), in LowerMemOpCallTo()
1465 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs()
1474 if (!StackPtr.getNode()) in PassF64ArgInRegs()
1570 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
[all …]
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelDAGToDAG.cpp87 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr; in hasBaseOrIndexReg()
95 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode())) in isRIPRelative()
109 if (Base_Reg.getNode()) in dump()
110 Base_Reg.getNode()->dump(); in dump()
116 if (IndexReg.getNode()) in dump()
117 IndexReg.getNode()->dump(); in dump()
280 if (AM.Segment.getNode()) in getAddressOperands()
395 if (Chain.getNode() == Load.getNode()) in MoveBelowOrigChain()
401 if (Chain.getOperand(i).getNode() == Load.getNode()) in MoveBelowOrigChain()
406 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load), MVT::Other, Ops); in MoveBelowOrigChain()
[all …]
HDX86ISelLowering.cpp1904 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), in getPICJumpTableRelocBase()
2024 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
2026 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
2029 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
2031 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
2060 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); in LowerReturn()
2072 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, in LowerReturn()
2114 if (Flag.getNode()) in LowerReturn()
2117 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps); in LowerReturn()
2215 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, in LowerCallResult()
[all …]
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp1136 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS); in emitComparison()
1170 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS) in emitComparison()
1178 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { in getAArch64Cmp()
1253 LHS.getNode()->hasNUsesOfValue(1, 0)) { in getAArch64Cmp()
1257 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS, in getAArch64Cmp()
1315 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS); in getAArch64XALUOOp()
1316 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS); in getAArch64XALUOOp()
1317 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
1318 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul, in getAArch64XALUOOp()
1324 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add); in getAArch64XALUOOp()
[all …]
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsSEISelLowering.cpp395 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); in selectMADD()
402 SDNode *MultNode = MultHi.getNode(); in selectMADD()
406 if (MultLo.getNode() != MultNode) in selectMADD()
431 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, in selectMADD()
438 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped, in selectMADD()
445 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); in selectMADD()
449 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); in selectMADD()
467 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); in selectMSUB()
474 SDNode *MultNode = MultHi.getNode(); in selectMSUB()
478 if (MultLo.getNode() != MultNode) in selectMSUB()
[all …]
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreISelLowering.cpp225 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); in LowerOperation()
266 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
271 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
273 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
304 GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining); in LowerGlobalAddress()
330 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, PtrVT, Result); in LowerBlockAddress()
348 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); in LowerConstantPool()
370 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index); in LowerBR_JT()
373 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, in LowerBR_JT()
375 return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT, in LowerBR_JT()
[all …]
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZSelectionDAGInfo.cpp42 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
45 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
109 Dst = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
114 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2); in EmitTargetCodeForMemset()
123 SDValue Dst2 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
128 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2); in EmitTargetCodeForMemset()
143 SDValue DstPlus1 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
166 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, in emitCLC()
169 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, in emitCLC()
178 SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue); in addIPMSequence()
[all …]
HDSystemZISelLowering.cpp811 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
814 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
818 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value); in convertLocVTToValVT()
827 Value = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i64, in convertLocVTToValVT()
829 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value); in convertLocVTToValVT()
842 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
844 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
846 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
852 Value = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Value); in convertValVTToLocVT()
853 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value, in convertValVTToLocVT()
[all …]
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp236 if (Flag.getNode()) in LowerReturn_32()
239 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps); in LowerReturn_32()
277 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
280 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
283 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
292 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, in LowerReturn_64()
298 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); in LowerReturn_64()
299 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); in LowerReturn_64()
315 if (Flag.getNode()) in LowerReturn_64()
318 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps); in LowerReturn_64()
[all …]
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp392 if (Flag.getNode()) in LowerReturn()
395 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps); in LowerReturn()
537 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
540 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
543 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
551 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr); in LowerCall()
575 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall()
641 if (InFlag.getNode()) in LowerCall()
646 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops); in LowerCall()
650 Chain = DAG.getNode(OpCode, dl, NodeTys, Ops); in LowerCall()
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/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp1086 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { in isFloatingPointZero()
1499 if (!UniquedVals[i&(Multiple-1)].getNode()) in get_VSPLTI_elt()
1514 if (!UniquedVals[i].getNode()) continue; // Must have been undefs. in get_VSPLTI_elt()
1521 if (!UniquedVals[Multiple-1].getNode()) in get_VSPLTI_elt()
1528 if (!UniquedVals[Multiple-1].getNode()) in get_VSPLTI_elt()
1541 if (!OpVal.getNode()) in get_VSPLTI_elt()
1547 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def. in get_VSPLTI_elt()
1629 return isIntS16Immediate(Op.getNode(), Imm); in isIntS16Immediate()
1893 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode())) in getPreIndexedAddressParts()
1972 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero); in LowerLabelRef()
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