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Searched refs:getDesc (Results 1 – 25 of 82) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
HDHexagonMCInstrInfo.cpp81 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAccessSize()
89 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getBitCount()
96 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getCExtOpNum()
100 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII, in getDesc() function in llvm::HexagonMCInstrInfo
107 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
125 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
131 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
139 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMaxValue()
154 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMinValue()
172 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
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HDHexagonShuffler.cpp144 MCInst const *ID = ISJ->getDesc(); in check()
176 if (HexagonMCInstrInfo::getDesc(MCII, *ID).isReturn()) in check()
193 if (HexagonMCInstrInfo::getDesc(MCII, *ID).isBranch()) in check()
199 if (HexagonMCInstrInfo::getDesc(MCII, *ID).mayLoad()) in check()
223 MCInst const *ID = ISJ->getDesc(); in check()
232 if (HexagonMCInstrInfo::getDesc(MCII, *ID).getOpcode() != Hexagon::A2_nop) in check()
242 if (HexagonMCInstrInfo::getDesc(MCII, *ID).isBranch() || in check()
243 HexagonMCInstrInfo::getDesc(MCII, *ID).isCall()) in check()
258 if (HexagonMCInstrInfo::getDesc(MCII, *ID).mayLoad()) { in check()
265 if (HexagonMCInstrInfo::getDesc(MCII, *ID).mayStore()) { in check()
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HDHexagonMCShuffler.cpp36 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
60 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
83 MCInst const *MI = I->getDesc(); in copyTo()
HDHexagonShuffler.h68 MCInst const *getDesc() const { return (ID); }; in getDesc() function
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMHazardRecognizer.cpp22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
43 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
46 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
HDARMBaseInstrInfo.cpp138 uint64_t TSFlags = MI->getDesc().TSFlags; in convertToThreeAddress()
158 const MCInstrDesc &MCID = MI->getDesc(); in convertToThreeAddress()
572 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) in isPredicable()
602 const MCInstrDesc &MCID = MI->getDesc(); in GetInstSizeInBytes()
1854 DefMI->getDesc(), DestReg); in optimizeSelect()
1857 const MCInstrDesc &DefDesc = DefMI->getDesc(); in optimizeSelect()
2101 const MCInstrDesc &Desc = MI.getDesc(); in rewriteARMFrameIndex()
2607 const MCInstrDesc &DefMCID = DefMI->getDesc(); in FoldImmediate()
2617 const MCInstrDesc &UseMCID = UseMI->getDesc(); in FoldImmediate()
2713 const MCInstrDesc &Desc = MI->getDesc(); in getNumMicroOpsSwiftLdSt()
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HDARMBaseRegisterInfo.cpp434 const MCInstrDesc &Desc = MI->getDesc(); in getFrameIndexInstrOffset()
623 const MCInstrDesc &Desc = MI->getDesc(); in isFrameOffsetLegal()
739 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || in eliminateFrameIndex()
740 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && in eliminateFrameIndex()
/NextBSD/contrib/llvm/lib/Support/
HDStatistic.cpp119 return std::strcmp(LHS->getDesc(), RHS->getDesc()) < 0; in PrintStatistics()
132 Stats.Stats[i]->getDesc()); in PrintStatistics()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonVLIWPacketizer.cpp378 return (MI->getDesc().isTerminator() || MI->getDesc().isCall()); in IsControlFlow()
409 const MCInstrDesc& TID = MI->getDesc(); in isCondInst()
491 if (MI->getDesc().mayLoad()) { in GetPostIncrementOperand()
497 if (MI->getDesc().mayStore()) { in GetPostIncrementOperand()
548 const MCInstrDesc& MCID = PacketMI->getDesc(); in CanPromoteToNewValueStore()
559 if (PacketSU->getInstr()->getDesc().mayStore() || in CanPromoteToNewValueStore()
576 MI->getDesc().mayStore() && in CanPromoteToNewValueStore()
582 PacketMI->getDesc().mayLoad() && in CanPromoteToNewValueStore()
960 const MCInstrDesc& TID = MI->getDesc(); in ignorePseudoInstruction()
995 const MCInstrDesc &MCIDI = I->getDesc(); in isLegalToPacketizeTogether()
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HDHexagonInstrInfo.cpp808 const MCInstrDesc &MID = MI->getDesc(); in isExtendable()
830 const uint64_t F = MI->getDesc().TSFlags; in isExtended()
844 return MI->getDesc().isBranch(); in isBranch()
858 const uint64_t F = MI->getDesc().TSFlags; in isNewValue()
872 bool isPred = MI->getDesc().isPredicable(); in isPredicable()
976 const uint64_t F = MI->getDesc().TSFlags; in isNewValueStore()
1096 const uint64_t F = MI->getDesc().TSFlags; in isPredicated()
1108 const uint64_t F = MI->getDesc().TSFlags; in isPredicatedTrue()
1125 const uint64_t F = MI->getDesc().TSFlags; in isPredicatedNew()
1140 const uint64_t F = MI->getDesc().TSFlags; in mayBeNewStore()
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/NextBSD/contrib/llvm/lib/CodeGen/
HDTargetInstrInfo.cpp125 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstruction()
153 MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { in commuteInstruction()
158 MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { in commuteInstruction()
196 const MCInstrDesc &MCID = MI->getDesc(); in findCommutedOpIndices()
230 const MCInstrDesc &MCID = MI->getDesc(); in PredicateInstruction()
767 unsigned Class = MI->getDesc().getSchedClass(); in getNumMicroOps()
802 return ItinData->getStageLatency(MI->getDesc().getSchedClass()); in getInstrLatency()
812 unsigned DefClass = DefMI->getDesc().getSchedClass(); in hasLowDefLatency()
823 unsigned DefClass = DefMI->getDesc().getSchedClass(); in getOperandLatency()
824 unsigned UseClass = UseMI->getDesc().getSchedClass(); in getOperandLatency()
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HDTargetSchedule.cpp79 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
105 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass()
168 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
212 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
HDPeepholeOptimizer.cpp272 assert(DefIdx < Def->getDesc().getNumDefs() && in ValueTracker()
883 assert(MI->getDesc().getNumDefs() == 1 && in optimizeCoalescableCopy()
996 const MCInstrDesc &MCID = MI->getDesc(); in isLoadFoldable()
1016 const MCInstrDesc &MCID = MI->getDesc(); in isMoveImmediate()
1037 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) { in foldImmediate()
1150 const MCInstrDesc &MIDesc = MI->getDesc(); in runOnMachineFunction()
1220 if (Def->getDesc().getNumDefs() != 1) in getNextSourceFromBitcast()
1412 (DefIdx < Def->getDesc().getNumDefs() || Def->getDesc().isVariadic()) && in getNextSourceImpl()
HDExecutionDepsFix.cpp512 const MCInstrDesc &MCID = MI->getDesc(); in processDefs()
585 for (unsigned i = mi->getDesc().getNumDefs(), in visitHardInstr()
586 e = mi->getDesc().getNumOperands(); i != e; ++i) { in visitHardInstr()
595 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitHardInstr()
614 for (unsigned i = mi->getDesc().getNumDefs(), in visitSoftInstr()
615 e = mi->getDesc().getNumOperands(); i != e; ++i) { in visitSoftInstr()
HDDFAPacketizer.cpp92 const llvm::MCInstrDesc &MID = MI->getDesc(); in canReserveResources()
99 const llvm::MCInstrDesc &MID = MI->getDesc(); in reserveResources()
HDCriticalAntiDepBreaker.cpp180 if (i < MI->getDesc().getNumOperands()) in PrescanInstruction()
181 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF); in PrescanInstruction()
295 if (i < MI->getDesc().getNumOperands()) in ScanInstruction()
296 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF); in ScanInstruction()
HDImplicitNullChecks.cpp241 Offset < PageSize && MI->getDesc().getNumDefs() == 1 && in analyzeBlockForNullChecks()
285 unsigned NumDefs = LoadMI->getDesc().getNumDefs(); in insertFaultingLoad()
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDMachineInstr.h264 const MCInstrDesc &getDesc() const { return *MCID; }
319 operands_begin(), operands_begin() + getDesc().getNumDefs());
323 operands_begin(), operands_begin() + getDesc().getNumDefs());
327 operands_begin() + getDesc().getNumDefs(), operands_end());
331 operands_begin() + getDesc().getNumDefs(), operands_end());
373 return getDesc().getFlags() & (1 << MCFlag);
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64DeadRegisterDefinitionsPass.cpp79 for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) { in processMachineBasicBlock()
99 switch (MI.getDesc().OpInfo[i].RegClass) { in processMachineBasicBlock()
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXInstrInfo.cpp72 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift; in isMoveInstr()
114 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift; in isLoadInstr()
125 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift; in isStoreInstr()
/NextBSD/contrib/llvm/include/llvm/Support/
HDRegistry.h36 const char *getDesc() const { return Desc; } in getDesc() function
53 static const char *descof(const entry &Entry) { return Entry.getDesc(); } in descof()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZInstrBuilder.h31 const MCInstrDesc &MCID = MI->getDesc(); in addFrameReference()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsInstrInfo.cpp264 return MI->getDesc().getSize(); in GetInstSizeInBytes()
283 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) in genInstrWithNewOpc()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetInstrInfo.h79 (MI->getDesc().isRematerializable() &&
630 assert(MI && MI->getDesc().isSelect() && "MI must be a select instruction"); in analyzeSelect()
949 return MI->getDesc().isPredicable(); in isPredicable()
/NextBSD/contrib/llvm/include/llvm/ADT/
HDStatistic.h44 const char *getDesc() const { return Desc; } in getDesc() function

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