1 /*-
2 * Copyright (c) 2015-2019 Mellanox Technologies. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: stable/12/sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c 371156 2021-12-06 15:56:25Z imp $
26 */
27
28 #include "en.h"
29 #include "port_buffer.h"
30
31 void
mlx5e_create_stats(struct sysctl_ctx_list * ctx,struct sysctl_oid_list * parent,const char * buffer,const char ** desc,unsigned num,u64 * arg)32 mlx5e_create_stats(struct sysctl_ctx_list *ctx,
33 struct sysctl_oid_list *parent, const char *buffer,
34 const char **desc, unsigned num, u64 * arg)
35 {
36 struct sysctl_oid *node;
37 unsigned x;
38
39 sysctl_ctx_init(ctx);
40
41 node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO,
42 buffer, CTLFLAG_RD, NULL, "Statistics");
43 if (node == NULL)
44 return;
45 for (x = 0; x != num; x++) {
46 SYSCTL_ADD_UQUAD(ctx, SYSCTL_CHILDREN(node), OID_AUTO,
47 desc[2 * x], CTLFLAG_RD, arg + x, desc[2 * x + 1]);
48 }
49 }
50
51 static void
mlx5e_ethtool_sync_tx_completion_fact(struct mlx5e_priv * priv)52 mlx5e_ethtool_sync_tx_completion_fact(struct mlx5e_priv *priv)
53 {
54 /*
55 * Limit the maximum distance between completion events to
56 * half of the currently set TX queue size.
57 *
58 * The maximum number of queue entries a single IP packet can
59 * consume is given by MLX5_SEND_WQE_MAX_WQEBBS.
60 *
61 * The worst case max value is then given as below:
62 */
63 uint64_t max = priv->params_ethtool.tx_queue_size /
64 (2 * MLX5_SEND_WQE_MAX_WQEBBS);
65
66 /*
67 * Update the maximum completion factor value in case the
68 * tx_queue_size field changed. Ensure we don't overflow
69 * 16-bits.
70 */
71 if (max < 1)
72 max = 1;
73 else if (max > 65535)
74 max = 65535;
75 priv->params_ethtool.tx_completion_fact_max = max;
76
77 /*
78 * Verify that the current TX completion factor is within the
79 * given limits:
80 */
81 if (priv->params_ethtool.tx_completion_fact < 1)
82 priv->params_ethtool.tx_completion_fact = 1;
83 else if (priv->params_ethtool.tx_completion_fact > max)
84 priv->params_ethtool.tx_completion_fact = max;
85 }
86
87 static int
mlx5e_getmaxrate(struct mlx5e_priv * priv)88 mlx5e_getmaxrate(struct mlx5e_priv *priv)
89 {
90 struct mlx5_core_dev *mdev = priv->mdev;
91 u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
92 u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
93 int err;
94 int i;
95
96 PRIV_LOCK(priv);
97 err = -mlx5_query_port_tc_rate_limit(mdev, max_bw_value, max_bw_unit);
98 if (err)
99 goto done;
100
101 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
102 switch (max_bw_unit[i]) {
103 case MLX5_100_MBPS_UNIT:
104 priv->params_ethtool.max_bw_value[i] = max_bw_value[i] * MLX5E_100MB;
105 break;
106 case MLX5_GBPS_UNIT:
107 priv->params_ethtool.max_bw_value[i] = max_bw_value[i] * MLX5E_1GB;
108 break;
109 case MLX5_BW_NO_LIMIT:
110 priv->params_ethtool.max_bw_value[i] = 0;
111 break;
112 default:
113 priv->params_ethtool.max_bw_value[i] = -1;
114 WARN_ONCE(true, "non-supported BW unit");
115 break;
116 }
117 }
118 done:
119 PRIV_UNLOCK(priv);
120 return (err);
121 }
122
123 static int
mlx5e_get_max_alloc(struct mlx5e_priv * priv)124 mlx5e_get_max_alloc(struct mlx5e_priv *priv)
125 {
126 struct mlx5_core_dev *mdev = priv->mdev;
127 int err;
128 int x;
129
130 PRIV_LOCK(priv);
131 err = -mlx5_query_port_tc_bw_alloc(mdev, priv->params_ethtool.max_bw_share);
132 if (err == 0) {
133 /* set default value */
134 for (x = 0; x != IEEE_8021QAZ_MAX_TCS; x++) {
135 priv->params_ethtool.max_bw_share[x] =
136 100 / IEEE_8021QAZ_MAX_TCS;
137 }
138 err = -mlx5_set_port_tc_bw_alloc(mdev,
139 priv->params_ethtool.max_bw_share);
140 }
141 PRIV_UNLOCK(priv);
142
143 return (err);
144 }
145
146 static int
mlx5e_get_dscp(struct mlx5e_priv * priv)147 mlx5e_get_dscp(struct mlx5e_priv *priv)
148 {
149 struct mlx5_core_dev *mdev = priv->mdev;
150 int err;
151
152 if (MLX5_CAP_GEN(mdev, qcam_reg) == 0 ||
153 MLX5_CAP_QCAM_REG(mdev, qpts) == 0 ||
154 MLX5_CAP_QCAM_REG(mdev, qpdpm) == 0)
155 return (EOPNOTSUPP);
156
157 PRIV_LOCK(priv);
158 err = -mlx5_query_dscp2prio(mdev, priv->params_ethtool.dscp2prio);
159 if (err)
160 goto done;
161
162 err = -mlx5_query_trust_state(mdev, &priv->params_ethtool.trust_state);
163 if (err)
164 goto done;
165 done:
166 PRIV_UNLOCK(priv);
167 return (err);
168 }
169
170 static void
mlx5e_tc_get_parameters(struct mlx5e_priv * priv,u64 * new_bw_value,u8 * max_bw_value,u8 * max_bw_unit)171 mlx5e_tc_get_parameters(struct mlx5e_priv *priv,
172 u64 *new_bw_value, u8 *max_bw_value, u8 *max_bw_unit)
173 {
174 const u64 upper_limit_mbps = 255 * MLX5E_100MB;
175 const u64 upper_limit_gbps = 255 * MLX5E_1GB;
176 u64 temp;
177 int i;
178
179 memset(max_bw_value, 0, IEEE_8021QAZ_MAX_TCS);
180 memset(max_bw_unit, 0, IEEE_8021QAZ_MAX_TCS);
181
182 for (i = 0; i <= mlx5_max_tc(priv->mdev); i++) {
183 temp = (new_bw_value != NULL) ?
184 new_bw_value[i] : priv->params_ethtool.max_bw_value[i];
185
186 if (!temp) {
187 max_bw_unit[i] = MLX5_BW_NO_LIMIT;
188 } else if (temp > upper_limit_gbps) {
189 max_bw_unit[i] = MLX5_BW_NO_LIMIT;
190 } else if (temp <= upper_limit_mbps) {
191 max_bw_value[i] = howmany(temp, MLX5E_100MB);
192 max_bw_unit[i] = MLX5_100_MBPS_UNIT;
193 } else {
194 max_bw_value[i] = howmany(temp, MLX5E_1GB);
195 max_bw_unit[i] = MLX5_GBPS_UNIT;
196 }
197 }
198 }
199
200 static int
mlx5e_tc_maxrate_handler(SYSCTL_HANDLER_ARGS)201 mlx5e_tc_maxrate_handler(SYSCTL_HANDLER_ARGS)
202 {
203 struct mlx5e_priv *priv = arg1;
204 struct mlx5_core_dev *mdev = priv->mdev;
205 u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
206 u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
207 u64 new_bw_value[IEEE_8021QAZ_MAX_TCS];
208 u8 max_rates = mlx5_max_tc(mdev) + 1;
209 u8 x;
210 int err;
211
212 PRIV_LOCK(priv);
213 err = SYSCTL_OUT(req, priv->params_ethtool.max_bw_value,
214 sizeof(priv->params_ethtool.max_bw_value[0]) * max_rates);
215 if (err || !req->newptr)
216 goto done;
217 err = SYSCTL_IN(req, new_bw_value,
218 sizeof(new_bw_value[0]) * max_rates);
219 if (err)
220 goto done;
221
222 /* range check input value */
223 for (x = 0; x != max_rates; x++) {
224 if (new_bw_value[x] % MLX5E_100MB) {
225 err = ERANGE;
226 goto done;
227 }
228 }
229
230 mlx5e_tc_get_parameters(priv, new_bw_value, max_bw_value, max_bw_unit);
231
232 err = -mlx5_modify_port_tc_rate_limit(mdev, max_bw_value, max_bw_unit);
233 if (err)
234 goto done;
235
236 memcpy(priv->params_ethtool.max_bw_value, new_bw_value,
237 sizeof(priv->params_ethtool.max_bw_value));
238 done:
239 PRIV_UNLOCK(priv);
240 return (err);
241 }
242
243 static int
mlx5e_tc_rate_share_handler(SYSCTL_HANDLER_ARGS)244 mlx5e_tc_rate_share_handler(SYSCTL_HANDLER_ARGS)
245 {
246 struct mlx5e_priv *priv = arg1;
247 struct mlx5_core_dev *mdev = priv->mdev;
248 u8 max_bw_share[IEEE_8021QAZ_MAX_TCS];
249 u8 max_rates = mlx5_max_tc(mdev) + 1;
250 int i;
251 int err;
252 int sum;
253
254 PRIV_LOCK(priv);
255 err = SYSCTL_OUT(req, priv->params_ethtool.max_bw_share, max_rates);
256 if (err || !req->newptr)
257 goto done;
258 err = SYSCTL_IN(req, max_bw_share, max_rates);
259 if (err)
260 goto done;
261
262 /* range check input value */
263 for (sum = i = 0; i != max_rates; i++) {
264 if (max_bw_share[i] < 1 || max_bw_share[i] > 100) {
265 err = ERANGE;
266 goto done;
267 }
268 sum += max_bw_share[i];
269 }
270
271 /* sum of values should be as close to 100 as possible */
272 if (sum < (100 - max_rates + 1) || sum > 100) {
273 err = ERANGE;
274 goto done;
275 }
276
277 err = -mlx5_set_port_tc_bw_alloc(mdev, max_bw_share);
278 if (err)
279 goto done;
280
281 memcpy(priv->params_ethtool.max_bw_share, max_bw_share,
282 sizeof(priv->params_ethtool.max_bw_share));
283 done:
284 PRIV_UNLOCK(priv);
285 return (err);
286 }
287
288 static int
mlx5e_get_prio_tc(struct mlx5e_priv * priv)289 mlx5e_get_prio_tc(struct mlx5e_priv *priv)
290 {
291 struct mlx5_core_dev *mdev = priv->mdev;
292 int err = 0;
293 int i;
294
295 PRIV_LOCK(priv);
296 if (!MLX5_CAP_GEN(priv->mdev, ets)) {
297 PRIV_UNLOCK(priv);
298 return (EOPNOTSUPP);
299 }
300
301 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
302 err = -mlx5_query_port_prio_tc(mdev, i, priv->params_ethtool.prio_tc + i);
303 if (err)
304 break;
305 }
306 PRIV_UNLOCK(priv);
307 return (err);
308 }
309
310 static int
mlx5e_prio_to_tc_handler(SYSCTL_HANDLER_ARGS)311 mlx5e_prio_to_tc_handler(SYSCTL_HANDLER_ARGS)
312 {
313 struct mlx5e_priv *priv = arg1;
314 struct mlx5_core_dev *mdev = priv->mdev;
315 uint8_t temp[MLX5E_MAX_PRIORITY];
316 int err;
317 int i;
318
319 PRIV_LOCK(priv);
320 err = SYSCTL_OUT(req, priv->params_ethtool.prio_tc, MLX5E_MAX_PRIORITY);
321 if (err || !req->newptr)
322 goto done;
323 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
324 if (err)
325 goto done;
326
327 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
328 if (temp[i] > mlx5_max_tc(mdev)) {
329 err = ERANGE;
330 goto done;
331 }
332 }
333
334 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
335 if (temp[i] == priv->params_ethtool.prio_tc[i])
336 continue;
337 err = -mlx5_set_port_prio_tc(mdev, i, temp[i]);
338 if (err)
339 goto done;
340 /* update cached value */
341 priv->params_ethtool.prio_tc[i] = temp[i];
342 }
343 done:
344 PRIV_UNLOCK(priv);
345 return (err);
346 }
347
348 int
mlx5e_fec_update(struct mlx5e_priv * priv)349 mlx5e_fec_update(struct mlx5e_priv *priv)
350 {
351 struct mlx5_core_dev *mdev = priv->mdev;
352 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
353 const int sz = MLX5_ST_SZ_BYTES(pplm_reg);
354 int err;
355
356 if (!MLX5_CAP_GEN(mdev, pcam_reg))
357 return (EOPNOTSUPP);
358
359 if (!MLX5_CAP_PCAM_REG(mdev, pplm))
360 return (EOPNOTSUPP);
361
362 MLX5_SET(pplm_reg, in, local_port, 1);
363
364 err = -mlx5_core_access_reg(mdev, in, sz, in, sz, MLX5_REG_PPLM, 0, 0);
365 if (err)
366 return (err);
367
368 /* get 10x..25x mask */
369 priv->params_ethtool.fec_mask_10x_25x[0] =
370 MLX5_GET(pplm_reg, in, fec_override_admin_10g_40g);
371 priv->params_ethtool.fec_mask_10x_25x[1] =
372 MLX5_GET(pplm_reg, in, fec_override_admin_25g) &
373 MLX5_GET(pplm_reg, in, fec_override_admin_50g);
374 priv->params_ethtool.fec_mask_10x_25x[2] =
375 MLX5_GET(pplm_reg, in, fec_override_admin_56g);
376 priv->params_ethtool.fec_mask_10x_25x[3] =
377 MLX5_GET(pplm_reg, in, fec_override_admin_100g);
378
379 /* get 10x..25x available bits */
380 priv->params_ethtool.fec_avail_10x_25x[0] =
381 MLX5_GET(pplm_reg, in, fec_override_cap_10g_40g);
382 priv->params_ethtool.fec_avail_10x_25x[1] =
383 MLX5_GET(pplm_reg, in, fec_override_cap_25g) &
384 MLX5_GET(pplm_reg, in, fec_override_cap_50g);
385 priv->params_ethtool.fec_avail_10x_25x[2] =
386 MLX5_GET(pplm_reg, in, fec_override_cap_56g);
387 priv->params_ethtool.fec_avail_10x_25x[3] =
388 MLX5_GET(pplm_reg, in, fec_override_cap_100g);
389
390 /* get 50x mask */
391 priv->params_ethtool.fec_mask_50x[0] =
392 MLX5_GET(pplm_reg, in, fec_override_admin_50g_1x);
393 priv->params_ethtool.fec_mask_50x[1] =
394 MLX5_GET(pplm_reg, in, fec_override_admin_100g_2x);
395 priv->params_ethtool.fec_mask_50x[2] =
396 MLX5_GET(pplm_reg, in, fec_override_admin_200g_4x);
397 priv->params_ethtool.fec_mask_50x[3] =
398 MLX5_GET(pplm_reg, in, fec_override_admin_400g_8x);
399
400 /* get 50x available bits */
401 priv->params_ethtool.fec_avail_50x[0] =
402 MLX5_GET(pplm_reg, in, fec_override_cap_50g_1x);
403 priv->params_ethtool.fec_avail_50x[1] =
404 MLX5_GET(pplm_reg, in, fec_override_cap_100g_2x);
405 priv->params_ethtool.fec_avail_50x[2] =
406 MLX5_GET(pplm_reg, in, fec_override_cap_200g_4x);
407 priv->params_ethtool.fec_avail_50x[3] =
408 MLX5_GET(pplm_reg, in, fec_override_cap_400g_8x);
409
410 /* get current FEC mask */
411 priv->params_ethtool.fec_mode_active =
412 MLX5_GET(pplm_reg, in, fec_mode_active);
413
414 return (0);
415 }
416
417 static int
mlx5e_fec_mask_10x_25x_handler(SYSCTL_HANDLER_ARGS)418 mlx5e_fec_mask_10x_25x_handler(SYSCTL_HANDLER_ARGS)
419 {
420 struct mlx5e_priv *priv = arg1;
421 struct mlx5_core_dev *mdev = priv->mdev;
422 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
423 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
424 const int sz = MLX5_ST_SZ_BYTES(pplm_reg);
425 u8 fec_mask_10x_25x[MLX5E_MAX_FEC_10X_25X];
426 u8 fec_cap_changed = 0;
427 u8 x;
428 int err;
429
430 PRIV_LOCK(priv);
431 err = SYSCTL_OUT(req, priv->params_ethtool.fec_mask_10x_25x,
432 sizeof(priv->params_ethtool.fec_mask_10x_25x));
433 if (err || !req->newptr)
434 goto done;
435
436 err = SYSCTL_IN(req, fec_mask_10x_25x,
437 sizeof(fec_mask_10x_25x));
438 if (err)
439 goto done;
440
441 if (!MLX5_CAP_GEN(mdev, pcam_reg)) {
442 err = EOPNOTSUPP;
443 goto done;
444 }
445
446 if (!MLX5_CAP_PCAM_REG(mdev, pplm)) {
447 err = EOPNOTSUPP;
448 goto done;
449 }
450
451 MLX5_SET(pplm_reg, in, local_port, 1);
452
453 err = -mlx5_core_access_reg(mdev, in, sz, in, sz, MLX5_REG_PPLM, 0, 0);
454 if (err)
455 goto done;
456
457 /* range check input value */
458 for (x = 0; x != MLX5E_MAX_FEC_10X_25X; x++) {
459 /* check only one bit is set, if any */
460 if (fec_mask_10x_25x[x] & (fec_mask_10x_25x[x] - 1)) {
461 err = ERANGE;
462 goto done;
463 }
464 /* check a supported bit is set, if any */
465 if (fec_mask_10x_25x[x] &
466 ~priv->params_ethtool.fec_avail_10x_25x[x]) {
467 err = ERANGE;
468 goto done;
469 }
470 fec_cap_changed |= (fec_mask_10x_25x[x] ^
471 priv->params_ethtool.fec_mask_10x_25x[x]);
472 }
473
474 /* check for no changes */
475 if (fec_cap_changed == 0)
476 goto done;
477
478 memset(in, 0, sizeof(in));
479
480 MLX5_SET(pplm_reg, in, local_port, 1);
481
482 /* set new values */
483 MLX5_SET(pplm_reg, in, fec_override_admin_10g_40g, fec_mask_10x_25x[0]);
484 MLX5_SET(pplm_reg, in, fec_override_admin_25g, fec_mask_10x_25x[1]);
485 MLX5_SET(pplm_reg, in, fec_override_admin_50g, fec_mask_10x_25x[1]);
486 MLX5_SET(pplm_reg, in, fec_override_admin_56g, fec_mask_10x_25x[2]);
487 MLX5_SET(pplm_reg, in, fec_override_admin_100g, fec_mask_10x_25x[3]);
488
489 /* preserve other values */
490 MLX5_SET(pplm_reg, in, fec_override_admin_50g_1x, priv->params_ethtool.fec_mask_50x[0]);
491 MLX5_SET(pplm_reg, in, fec_override_admin_100g_2x, priv->params_ethtool.fec_mask_50x[1]);
492 MLX5_SET(pplm_reg, in, fec_override_admin_200g_4x, priv->params_ethtool.fec_mask_50x[2]);
493 MLX5_SET(pplm_reg, in, fec_override_admin_400g_8x, priv->params_ethtool.fec_mask_50x[3]);
494
495 /* send new value to the firmware */
496 err = -mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPLM, 0, 1);
497 if (err)
498 goto done;
499
500 memcpy(priv->params_ethtool.fec_mask_10x_25x, fec_mask_10x_25x,
501 sizeof(priv->params_ethtool.fec_mask_10x_25x));
502
503 mlx5_toggle_port_link(priv->mdev);
504 done:
505 PRIV_UNLOCK(priv);
506 return (err);
507 }
508
509 static int
mlx5e_fec_avail_10x_25x_handler(SYSCTL_HANDLER_ARGS)510 mlx5e_fec_avail_10x_25x_handler(SYSCTL_HANDLER_ARGS)
511 {
512 struct mlx5e_priv *priv = arg1;
513 int err;
514
515 PRIV_LOCK(priv);
516 err = SYSCTL_OUT(req, priv->params_ethtool.fec_avail_10x_25x,
517 sizeof(priv->params_ethtool.fec_avail_10x_25x));
518 PRIV_UNLOCK(priv);
519 return (err);
520 }
521
522 static int
mlx5e_fec_mask_50x_handler(SYSCTL_HANDLER_ARGS)523 mlx5e_fec_mask_50x_handler(SYSCTL_HANDLER_ARGS)
524 {
525 struct mlx5e_priv *priv = arg1;
526 struct mlx5_core_dev *mdev = priv->mdev;
527 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
528 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
529 const int sz = MLX5_ST_SZ_BYTES(pplm_reg);
530 u16 fec_mask_50x[MLX5E_MAX_FEC_50X];
531 u16 fec_cap_changed = 0;
532 u8 x;
533 int err;
534
535 PRIV_LOCK(priv);
536 err = SYSCTL_OUT(req, priv->params_ethtool.fec_mask_50x,
537 sizeof(priv->params_ethtool.fec_mask_50x));
538 if (err || !req->newptr)
539 goto done;
540
541 err = SYSCTL_IN(req, fec_mask_50x,
542 sizeof(fec_mask_50x));
543 if (err)
544 goto done;
545
546 if (!MLX5_CAP_GEN(mdev, pcam_reg)) {
547 err = EOPNOTSUPP;
548 goto done;
549 }
550
551 if (!MLX5_CAP_PCAM_REG(mdev, pplm)) {
552 err = EOPNOTSUPP;
553 goto done;
554 }
555
556 MLX5_SET(pplm_reg, in, local_port, 1);
557
558 err = -mlx5_core_access_reg(mdev, in, sz, in, sz, MLX5_REG_PPLM, 0, 0);
559 if (err)
560 goto done;
561
562 /* range check input value */
563 for (x = 0; x != MLX5E_MAX_FEC_50X; x++) {
564 /* check only one bit is set, if any */
565 if (fec_mask_50x[x] & (fec_mask_50x[x] - 1)) {
566 err = ERANGE;
567 goto done;
568 }
569 /* check a supported bit is set, if any */
570 if (fec_mask_50x[x] &
571 ~priv->params_ethtool.fec_avail_50x[x]) {
572 err = ERANGE;
573 goto done;
574 }
575 fec_cap_changed |= (fec_mask_50x[x] ^
576 priv->params_ethtool.fec_mask_50x[x]);
577 }
578
579 /* check for no changes */
580 if (fec_cap_changed == 0)
581 goto done;
582
583 memset(in, 0, sizeof(in));
584
585 MLX5_SET(pplm_reg, in, local_port, 1);
586
587 /* set new values */
588 MLX5_SET(pplm_reg, in, fec_override_admin_50g_1x, fec_mask_50x[0]);
589 MLX5_SET(pplm_reg, in, fec_override_admin_100g_2x, fec_mask_50x[1]);
590 MLX5_SET(pplm_reg, in, fec_override_admin_200g_4x, fec_mask_50x[2]);
591 MLX5_SET(pplm_reg, in, fec_override_admin_400g_8x, fec_mask_50x[3]);
592
593 /* preserve other values */
594 MLX5_SET(pplm_reg, in, fec_override_admin_10g_40g, priv->params_ethtool.fec_mask_10x_25x[0]);
595 MLX5_SET(pplm_reg, in, fec_override_admin_25g, priv->params_ethtool.fec_mask_10x_25x[1]);
596 MLX5_SET(pplm_reg, in, fec_override_admin_50g, priv->params_ethtool.fec_mask_10x_25x[1]);
597 MLX5_SET(pplm_reg, in, fec_override_admin_56g, priv->params_ethtool.fec_mask_10x_25x[2]);
598 MLX5_SET(pplm_reg, in, fec_override_admin_100g, priv->params_ethtool.fec_mask_10x_25x[3]);
599
600 /* send new value to the firmware */
601 err = -mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPLM, 0, 1);
602 if (err)
603 goto done;
604
605 memcpy(priv->params_ethtool.fec_mask_50x, fec_mask_50x,
606 sizeof(priv->params_ethtool.fec_mask_50x));
607
608 mlx5_toggle_port_link(priv->mdev);
609 done:
610 PRIV_UNLOCK(priv);
611 return (err);
612 }
613
614 static int
mlx5e_fec_avail_50x_handler(SYSCTL_HANDLER_ARGS)615 mlx5e_fec_avail_50x_handler(SYSCTL_HANDLER_ARGS)
616 {
617 struct mlx5e_priv *priv = arg1;
618 int err;
619
620 PRIV_LOCK(priv);
621 err = SYSCTL_OUT(req, priv->params_ethtool.fec_avail_50x,
622 sizeof(priv->params_ethtool.fec_avail_50x));
623 PRIV_UNLOCK(priv);
624 return (err);
625 }
626
627 static int
mlx5e_trust_state_handler(SYSCTL_HANDLER_ARGS)628 mlx5e_trust_state_handler(SYSCTL_HANDLER_ARGS)
629 {
630 struct mlx5e_priv *priv = arg1;
631 struct mlx5_core_dev *mdev = priv->mdev;
632 int err;
633 u8 result;
634
635 PRIV_LOCK(priv);
636 result = priv->params_ethtool.trust_state;
637 err = sysctl_handle_8(oidp, &result, 0, req);
638 if (err || !req->newptr ||
639 result == priv->params_ethtool.trust_state)
640 goto done;
641
642 switch (result) {
643 case MLX5_QPTS_TRUST_PCP:
644 case MLX5_QPTS_TRUST_DSCP:
645 break;
646 case MLX5_QPTS_TRUST_BOTH:
647 if (!MLX5_CAP_QCAM_FEATURE(mdev, qpts_trust_both)) {
648 err = EOPNOTSUPP;
649 goto done;
650 }
651 break;
652 default:
653 err = ERANGE;
654 goto done;
655 }
656
657 err = -mlx5_set_trust_state(mdev, result);
658 if (err)
659 goto done;
660
661 priv->params_ethtool.trust_state = result;
662
663 /* update inline mode */
664 mlx5e_refresh_sq_inline(priv);
665 #ifdef RATELIMIT
666 mlx5e_rl_refresh_sq_inline(&priv->rl);
667 #endif
668 done:
669 PRIV_UNLOCK(priv);
670 return (err);
671 }
672
673 static int
mlx5e_dscp_prio_handler(SYSCTL_HANDLER_ARGS)674 mlx5e_dscp_prio_handler(SYSCTL_HANDLER_ARGS)
675 {
676 struct mlx5e_priv *priv = arg1;
677 int prio_index = arg2;
678 struct mlx5_core_dev *mdev = priv->mdev;
679 uint8_t dscp2prio[MLX5_MAX_SUPPORTED_DSCP];
680 uint8_t x;
681 int err;
682
683 PRIV_LOCK(priv);
684 err = SYSCTL_OUT(req, priv->params_ethtool.dscp2prio + prio_index,
685 sizeof(priv->params_ethtool.dscp2prio) / 8);
686 if (err || !req->newptr)
687 goto done;
688
689 memcpy(dscp2prio, priv->params_ethtool.dscp2prio, sizeof(dscp2prio));
690 err = SYSCTL_IN(req, dscp2prio + prio_index, sizeof(dscp2prio) / 8);
691 if (err)
692 goto done;
693 for (x = 0; x != MLX5_MAX_SUPPORTED_DSCP; x++) {
694 if (dscp2prio[x] > 7) {
695 err = ERANGE;
696 goto done;
697 }
698 }
699 err = -mlx5_set_dscp2prio(mdev, dscp2prio);
700 if (err)
701 goto done;
702
703 /* update local array */
704 memcpy(priv->params_ethtool.dscp2prio, dscp2prio,
705 sizeof(priv->params_ethtool.dscp2prio));
706 done:
707 PRIV_UNLOCK(priv);
708 return (err);
709 }
710
711 int
mlx5e_update_buf_lossy(struct mlx5e_priv * priv)712 mlx5e_update_buf_lossy(struct mlx5e_priv *priv)
713 {
714 struct ieee_pfc pfc;
715
716 PRIV_ASSERT_LOCKED(priv);
717 bzero(&pfc, sizeof(pfc));
718 pfc.pfc_en = priv->params.rx_priority_flow_control;
719 return (-mlx5e_port_manual_buffer_config(priv, MLX5E_PORT_BUFFER_PFC,
720 priv->params_ethtool.hw_mtu, &pfc, NULL, NULL));
721 }
722
723 static int
mlx5e_buf_size_handler(SYSCTL_HANDLER_ARGS)724 mlx5e_buf_size_handler(SYSCTL_HANDLER_ARGS)
725 {
726 struct mlx5e_priv *priv;
727 u32 buf_size[MLX5E_MAX_BUFFER];
728 struct mlx5e_port_buffer port_buffer;
729 int error, i;
730
731 priv = arg1;
732 PRIV_LOCK(priv);
733 error = -mlx5e_port_query_buffer(priv, &port_buffer);
734 if (error != 0)
735 goto done;
736 for (i = 0; i < nitems(buf_size); i++)
737 buf_size[i] = port_buffer.buffer[i].size;
738 error = SYSCTL_OUT(req, buf_size, sizeof(buf_size));
739 if (error != 0 || req->newptr == NULL)
740 goto done;
741 error = SYSCTL_IN(req, buf_size, sizeof(buf_size));
742 if (error != 0)
743 goto done;
744 error = -mlx5e_port_manual_buffer_config(priv, MLX5E_PORT_BUFFER_SIZE,
745 priv->params_ethtool.hw_mtu, NULL, buf_size, NULL);
746 done:
747 PRIV_UNLOCK(priv);
748 return (error);
749 }
750
751 static int
mlx5e_buf_prio_handler(SYSCTL_HANDLER_ARGS)752 mlx5e_buf_prio_handler(SYSCTL_HANDLER_ARGS)
753 {
754 struct mlx5e_priv *priv;
755 struct mlx5_core_dev *mdev;
756 u8 buffer[MLX5E_MAX_BUFFER];
757 int error;
758
759 priv = arg1;
760 mdev = priv->mdev;
761 PRIV_LOCK(priv);
762 error = -mlx5e_port_query_priority2buffer(mdev, buffer);
763 if (error != 0)
764 goto done;
765 error = SYSCTL_OUT(req, buffer, MLX5E_MAX_BUFFER);
766 if (error != 0 || req->newptr == NULL)
767 goto done;
768 error = SYSCTL_IN(req, buffer, MLX5E_MAX_BUFFER);
769 if (error != 0)
770 goto done;
771 error = -mlx5e_port_manual_buffer_config(priv,
772 MLX5E_PORT_BUFFER_PRIO2BUFFER,
773 priv->params_ethtool.hw_mtu, NULL, NULL, buffer);
774 if (error == 0)
775 error = mlx5e_update_buf_lossy(priv);
776 done:
777 PRIV_UNLOCK(priv);
778 return (error);
779 }
780
781 static int
mlx5e_cable_length_handler(SYSCTL_HANDLER_ARGS)782 mlx5e_cable_length_handler(SYSCTL_HANDLER_ARGS)
783 {
784 struct mlx5e_priv *priv;
785 u_int cable_len;
786 int error;
787
788 priv = arg1;
789 PRIV_LOCK(priv);
790 cable_len = priv->dcbx.cable_len;
791 error = sysctl_handle_int(oidp, &cable_len, 0, req);
792 if (error == 0 && req->newptr != NULL &&
793 cable_len != priv->dcbx.cable_len) {
794 error = -mlx5e_port_manual_buffer_config(priv,
795 MLX5E_PORT_BUFFER_CABLE_LEN, priv->params_ethtool.hw_mtu,
796 NULL, NULL, NULL);
797 if (error == 0)
798 priv->dcbx.cable_len = cable_len;
799 }
800 PRIV_UNLOCK(priv);
801 return (error);
802 }
803
804 static int
mlx5e_hw_temperature_handler(SYSCTL_HANDLER_ARGS)805 mlx5e_hw_temperature_handler(SYSCTL_HANDLER_ARGS)
806 {
807 struct mlx5e_priv *priv = arg1;
808 int err;
809
810 PRIV_LOCK(priv);
811 err = SYSCTL_OUT(req, priv->params_ethtool.hw_val_temp,
812 sizeof(priv->params_ethtool.hw_val_temp[0]) *
813 priv->params_ethtool.hw_num_temp);
814 if (err == 0 && req->newptr != NULL)
815 err = EOPNOTSUPP;
816 PRIV_UNLOCK(priv);
817 return (err);
818 }
819
820 int
mlx5e_hw_temperature_update(struct mlx5e_priv * priv)821 mlx5e_hw_temperature_update(struct mlx5e_priv *priv)
822 {
823 int err;
824 u32 x;
825
826 if (priv->params_ethtool.hw_num_temp == 0) {
827 u32 out_cap[MLX5_ST_SZ_DW(mtcap)] = {};
828 const int sz_cap = MLX5_ST_SZ_BYTES(mtcap);
829 u32 value;
830
831 err = -mlx5_core_access_reg(priv->mdev, NULL, 0, out_cap, sz_cap,
832 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP, 0, 0);
833 if (err)
834 goto done;
835 value = MLX5_GET(mtcap, out_cap, sensor_count);
836 if (value == 0)
837 return (0);
838 if (value > MLX5_MAX_TEMPERATURE)
839 value = MLX5_MAX_TEMPERATURE;
840 /* update number of temperature sensors */
841 priv->params_ethtool.hw_num_temp = value;
842 }
843
844 for (x = 0; x != priv->params_ethtool.hw_num_temp; x++) {
845 u32 out_sensor[MLX5_ST_SZ_DW(mtmp_reg)] = {};
846 const int sz_sensor = MLX5_ST_SZ_BYTES(mtmp_reg);
847
848 MLX5_SET(mtmp_reg, out_sensor, sensor_index, x);
849
850 err = -mlx5_core_access_reg(priv->mdev, out_sensor, sz_sensor,
851 out_sensor, sz_sensor,
852 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP, 0, 0);
853 if (err)
854 goto done;
855 /* convert from 0.125 celsius to millicelsius */
856 priv->params_ethtool.hw_val_temp[x] =
857 (s16)MLX5_GET(mtmp_reg, out_sensor, temperature) * 125;
858 }
859 done:
860 return (err);
861 }
862
863 #define MLX5_PARAM_OFFSET(n) \
864 __offsetof(struct mlx5e_priv, params_ethtool.n)
865
866 static int
mlx5e_ethtool_handler(SYSCTL_HANDLER_ARGS)867 mlx5e_ethtool_handler(SYSCTL_HANDLER_ARGS)
868 {
869 struct mlx5e_priv *priv = arg1;
870 uint64_t value;
871 int mode_modify;
872 int was_opened;
873 int error;
874
875 PRIV_LOCK(priv);
876 value = priv->params_ethtool.arg[arg2];
877 if (req != NULL) {
878 error = sysctl_handle_64(oidp, &value, 0, req);
879 if (error || req->newptr == NULL ||
880 value == priv->params_ethtool.arg[arg2])
881 goto done;
882
883 /* assign new value */
884 priv->params_ethtool.arg[arg2] = value;
885 } else {
886 error = 0;
887 }
888 /* check if device is gone */
889 if (priv->gone) {
890 error = ENXIO;
891 goto done;
892 }
893 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
894 mode_modify = MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify);
895
896 switch (MLX5_PARAM_OFFSET(arg[arg2])) {
897 case MLX5_PARAM_OFFSET(rx_coalesce_usecs):
898 /* import RX coal time */
899 if (priv->params_ethtool.rx_coalesce_usecs < 1)
900 priv->params_ethtool.rx_coalesce_usecs = 0;
901 else if (priv->params_ethtool.rx_coalesce_usecs >
902 MLX5E_FLD_MAX(cqc, cq_period)) {
903 priv->params_ethtool.rx_coalesce_usecs =
904 MLX5E_FLD_MAX(cqc, cq_period);
905 }
906 priv->params.rx_cq_moderation_usec =
907 priv->params_ethtool.rx_coalesce_usecs;
908
909 /* check to avoid down and up the network interface */
910 if (was_opened)
911 error = mlx5e_refresh_channel_params(priv);
912 break;
913
914 case MLX5_PARAM_OFFSET(rx_coalesce_pkts):
915 /* import RX coal pkts */
916 if (priv->params_ethtool.rx_coalesce_pkts < 1)
917 priv->params_ethtool.rx_coalesce_pkts = 0;
918 else if (priv->params_ethtool.rx_coalesce_pkts >
919 MLX5E_FLD_MAX(cqc, cq_max_count)) {
920 priv->params_ethtool.rx_coalesce_pkts =
921 MLX5E_FLD_MAX(cqc, cq_max_count);
922 }
923 priv->params.rx_cq_moderation_pkts =
924 priv->params_ethtool.rx_coalesce_pkts;
925
926 /* check to avoid down and up the network interface */
927 if (was_opened)
928 error = mlx5e_refresh_channel_params(priv);
929 break;
930
931 case MLX5_PARAM_OFFSET(tx_coalesce_usecs):
932 /* import TX coal time */
933 if (priv->params_ethtool.tx_coalesce_usecs < 1)
934 priv->params_ethtool.tx_coalesce_usecs = 0;
935 else if (priv->params_ethtool.tx_coalesce_usecs >
936 MLX5E_FLD_MAX(cqc, cq_period)) {
937 priv->params_ethtool.tx_coalesce_usecs =
938 MLX5E_FLD_MAX(cqc, cq_period);
939 }
940 priv->params.tx_cq_moderation_usec =
941 priv->params_ethtool.tx_coalesce_usecs;
942
943 /* check to avoid down and up the network interface */
944 if (was_opened)
945 error = mlx5e_refresh_channel_params(priv);
946 break;
947
948 case MLX5_PARAM_OFFSET(tx_coalesce_pkts):
949 /* import TX coal pkts */
950 if (priv->params_ethtool.tx_coalesce_pkts < 1)
951 priv->params_ethtool.tx_coalesce_pkts = 0;
952 else if (priv->params_ethtool.tx_coalesce_pkts >
953 MLX5E_FLD_MAX(cqc, cq_max_count)) {
954 priv->params_ethtool.tx_coalesce_pkts =
955 MLX5E_FLD_MAX(cqc, cq_max_count);
956 }
957 priv->params.tx_cq_moderation_pkts =
958 priv->params_ethtool.tx_coalesce_pkts;
959
960 /* check to avoid down and up the network interface */
961 if (was_opened)
962 error = mlx5e_refresh_channel_params(priv);
963 break;
964
965 case MLX5_PARAM_OFFSET(tx_queue_size):
966 /* network interface must be down */
967 if (was_opened)
968 mlx5e_close_locked(priv->ifp);
969
970 /* import TX queue size */
971 if (priv->params_ethtool.tx_queue_size <
972 (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
973 priv->params_ethtool.tx_queue_size =
974 (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
975 } else if (priv->params_ethtool.tx_queue_size >
976 priv->params_ethtool.tx_queue_size_max) {
977 priv->params_ethtool.tx_queue_size =
978 priv->params_ethtool.tx_queue_size_max;
979 }
980 /* store actual TX queue size */
981 priv->params.log_sq_size =
982 order_base_2(priv->params_ethtool.tx_queue_size);
983 priv->params_ethtool.tx_queue_size =
984 1 << priv->params.log_sq_size;
985
986 /* verify TX completion factor */
987 mlx5e_ethtool_sync_tx_completion_fact(priv);
988
989 /* restart network interface, if any */
990 if (was_opened)
991 mlx5e_open_locked(priv->ifp);
992 break;
993
994 case MLX5_PARAM_OFFSET(rx_queue_size):
995 /* network interface must be down */
996 if (was_opened)
997 mlx5e_close_locked(priv->ifp);
998
999 /* import RX queue size */
1000 if (priv->params_ethtool.rx_queue_size <
1001 (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
1002 priv->params_ethtool.rx_queue_size =
1003 (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
1004 } else if (priv->params_ethtool.rx_queue_size >
1005 priv->params_ethtool.rx_queue_size_max) {
1006 priv->params_ethtool.rx_queue_size =
1007 priv->params_ethtool.rx_queue_size_max;
1008 }
1009 /* store actual RX queue size */
1010 priv->params.log_rq_size =
1011 order_base_2(priv->params_ethtool.rx_queue_size);
1012 priv->params_ethtool.rx_queue_size =
1013 1 << priv->params.log_rq_size;
1014
1015 /* update least number of RX WQEs */
1016 priv->params.min_rx_wqes = min(
1017 priv->params_ethtool.rx_queue_size - 1,
1018 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES);
1019
1020 /* restart network interface, if any */
1021 if (was_opened)
1022 mlx5e_open_locked(priv->ifp);
1023 break;
1024
1025 case MLX5_PARAM_OFFSET(channels_rsss):
1026 /* network interface must be down */
1027 if (was_opened)
1028 mlx5e_close_locked(priv->ifp);
1029
1030 /* import number of channels */
1031 if (priv->params_ethtool.channels_rsss < 1)
1032 priv->params_ethtool.channels_rsss = 1;
1033 else if (priv->params_ethtool.channels_rsss > 128)
1034 priv->params_ethtool.channels_rsss = 128;
1035
1036 priv->params.channels_rsss = priv->params_ethtool.channels_rsss;
1037
1038 /* restart network interface, if any */
1039 if (was_opened)
1040 mlx5e_open_locked(priv->ifp);
1041 break;
1042
1043 case MLX5_PARAM_OFFSET(channels):
1044 /* network interface must be down */
1045 if (was_opened)
1046 mlx5e_close_locked(priv->ifp);
1047
1048 /* import number of channels */
1049 if (priv->params_ethtool.channels < 1)
1050 priv->params_ethtool.channels = 1;
1051 else if (priv->params_ethtool.channels >
1052 (u64) priv->mdev->priv.eq_table.num_comp_vectors) {
1053 priv->params_ethtool.channels =
1054 (u64) priv->mdev->priv.eq_table.num_comp_vectors;
1055 }
1056 priv->params.num_channels = priv->params_ethtool.channels;
1057
1058 /* restart network interface, if any */
1059 if (was_opened)
1060 mlx5e_open_locked(priv->ifp);
1061 break;
1062
1063 case MLX5_PARAM_OFFSET(rx_coalesce_mode):
1064 /* network interface must be down */
1065 if (was_opened != 0 && mode_modify == 0)
1066 mlx5e_close_locked(priv->ifp);
1067
1068 /* import RX coalesce mode */
1069 if (priv->params_ethtool.rx_coalesce_mode > 3)
1070 priv->params_ethtool.rx_coalesce_mode = 3;
1071 priv->params.rx_cq_moderation_mode =
1072 priv->params_ethtool.rx_coalesce_mode;
1073
1074 /* restart network interface, if any */
1075 if (was_opened != 0) {
1076 if (mode_modify == 0)
1077 mlx5e_open_locked(priv->ifp);
1078 else
1079 error = mlx5e_refresh_channel_params(priv);
1080 }
1081 break;
1082
1083 case MLX5_PARAM_OFFSET(tx_coalesce_mode):
1084 /* network interface must be down */
1085 if (was_opened != 0 && mode_modify == 0)
1086 mlx5e_close_locked(priv->ifp);
1087
1088 /* import TX coalesce mode */
1089 if (priv->params_ethtool.tx_coalesce_mode != 0)
1090 priv->params_ethtool.tx_coalesce_mode = 1;
1091 priv->params.tx_cq_moderation_mode =
1092 priv->params_ethtool.tx_coalesce_mode;
1093
1094 /* restart network interface, if any */
1095 if (was_opened != 0) {
1096 if (mode_modify == 0)
1097 mlx5e_open_locked(priv->ifp);
1098 else
1099 error = mlx5e_refresh_channel_params(priv);
1100 }
1101 break;
1102
1103 case MLX5_PARAM_OFFSET(hw_lro):
1104 /* network interface must be down */
1105 if (was_opened)
1106 mlx5e_close_locked(priv->ifp);
1107
1108 /* import HW LRO mode */
1109 if (priv->params_ethtool.hw_lro != 0 &&
1110 MLX5_CAP_ETH(priv->mdev, lro_cap)) {
1111 priv->params_ethtool.hw_lro = 1;
1112 /* check if feature should actually be enabled */
1113 if (priv->ifp->if_capenable & IFCAP_LRO) {
1114 priv->params.hw_lro_en = true;
1115 } else {
1116 priv->params.hw_lro_en = false;
1117
1118 mlx5_en_warn(priv->ifp, "To enable HW LRO "
1119 "please also enable LRO via ifconfig(8).\n");
1120 }
1121 } else {
1122 /* return an error if HW does not support this feature */
1123 if (priv->params_ethtool.hw_lro != 0)
1124 error = EINVAL;
1125 priv->params.hw_lro_en = false;
1126 priv->params_ethtool.hw_lro = 0;
1127 }
1128 /* restart network interface, if any */
1129 if (was_opened)
1130 mlx5e_open_locked(priv->ifp);
1131 break;
1132
1133 case MLX5_PARAM_OFFSET(cqe_zipping):
1134 /* network interface must be down */
1135 if (was_opened)
1136 mlx5e_close_locked(priv->ifp);
1137
1138 /* import CQE zipping mode */
1139 if (priv->params_ethtool.cqe_zipping &&
1140 MLX5_CAP_GEN(priv->mdev, cqe_compression)) {
1141 priv->params.cqe_zipping_en = true;
1142 priv->params_ethtool.cqe_zipping = 1;
1143 } else {
1144 priv->params.cqe_zipping_en = false;
1145 priv->params_ethtool.cqe_zipping = 0;
1146 }
1147 /* restart network interface, if any */
1148 if (was_opened)
1149 mlx5e_open_locked(priv->ifp);
1150 break;
1151
1152 case MLX5_PARAM_OFFSET(tx_completion_fact):
1153 /* network interface must be down */
1154 if (was_opened)
1155 mlx5e_close_locked(priv->ifp);
1156
1157 /* verify parameter */
1158 mlx5e_ethtool_sync_tx_completion_fact(priv);
1159
1160 /* restart network interface, if any */
1161 if (was_opened)
1162 mlx5e_open_locked(priv->ifp);
1163 break;
1164
1165 case MLX5_PARAM_OFFSET(modify_tx_dma):
1166 /* check if network interface is opened */
1167 if (was_opened) {
1168 priv->params_ethtool.modify_tx_dma =
1169 priv->params_ethtool.modify_tx_dma ? 1 : 0;
1170 /* modify tx according to value */
1171 mlx5e_modify_tx_dma(priv, value != 0);
1172 } else {
1173 /* if closed force enable tx */
1174 priv->params_ethtool.modify_tx_dma = 0;
1175 }
1176 break;
1177
1178 case MLX5_PARAM_OFFSET(modify_rx_dma):
1179 /* check if network interface is opened */
1180 if (was_opened) {
1181 priv->params_ethtool.modify_rx_dma =
1182 priv->params_ethtool.modify_rx_dma ? 1 : 0;
1183 /* modify rx according to value */
1184 mlx5e_modify_rx_dma(priv, value != 0);
1185 } else {
1186 /* if closed force enable rx */
1187 priv->params_ethtool.modify_rx_dma = 0;
1188 }
1189 break;
1190
1191 case MLX5_PARAM_OFFSET(diag_pci_enable):
1192 priv->params_ethtool.diag_pci_enable =
1193 priv->params_ethtool.diag_pci_enable ? 1 : 0;
1194
1195 error = -mlx5_core_set_diagnostics_full(priv->mdev,
1196 priv->params_ethtool.diag_pci_enable,
1197 priv->params_ethtool.diag_general_enable);
1198 break;
1199
1200 case MLX5_PARAM_OFFSET(diag_general_enable):
1201 priv->params_ethtool.diag_general_enable =
1202 priv->params_ethtool.diag_general_enable ? 1 : 0;
1203
1204 error = -mlx5_core_set_diagnostics_full(priv->mdev,
1205 priv->params_ethtool.diag_pci_enable,
1206 priv->params_ethtool.diag_general_enable);
1207 break;
1208
1209 case MLX5_PARAM_OFFSET(mc_local_lb):
1210 priv->params_ethtool.mc_local_lb =
1211 priv->params_ethtool.mc_local_lb ? 1 : 0;
1212
1213 if (MLX5_CAP_GEN(priv->mdev, disable_local_lb)) {
1214 error = mlx5_nic_vport_modify_local_lb(priv->mdev,
1215 MLX5_LOCAL_MC_LB, priv->params_ethtool.mc_local_lb);
1216 } else {
1217 error = EOPNOTSUPP;
1218 }
1219 break;
1220
1221 case MLX5_PARAM_OFFSET(uc_local_lb):
1222 priv->params_ethtool.uc_local_lb =
1223 priv->params_ethtool.uc_local_lb ? 1 : 0;
1224
1225 if (MLX5_CAP_GEN(priv->mdev, disable_local_lb)) {
1226 error = mlx5_nic_vport_modify_local_lb(priv->mdev,
1227 MLX5_LOCAL_UC_LB, priv->params_ethtool.uc_local_lb);
1228 } else {
1229 error = EOPNOTSUPP;
1230 }
1231 break;
1232
1233 default:
1234 break;
1235 }
1236 done:
1237 PRIV_UNLOCK(priv);
1238 return (error);
1239 }
1240
1241 static const char *mlx5e_params_desc[] = {
1242 MLX5E_PARAMS(MLX5E_STATS_DESC)
1243 };
1244
1245 static const char *mlx5e_port_stats_debug_desc[] = {
1246 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_DESC)
1247 };
1248
1249 static int
mlx5e_ethtool_debug_channel_info(SYSCTL_HANDLER_ARGS)1250 mlx5e_ethtool_debug_channel_info(SYSCTL_HANDLER_ARGS)
1251 {
1252 struct mlx5e_priv *priv;
1253 struct sbuf sb;
1254 struct mlx5e_channel *c;
1255 struct mlx5e_sq *sq;
1256 struct mlx5e_rq *rq;
1257 int error, i, tc;
1258 bool opened;
1259
1260 priv = arg1;
1261 error = sysctl_wire_old_buffer(req, 0);
1262 if (error != 0)
1263 return (error);
1264 if (sbuf_new_for_sysctl(&sb, NULL, 1024, req) == NULL)
1265 return (ENOMEM);
1266 sbuf_clear_flags(&sb, SBUF_INCLUDENUL);
1267
1268 PRIV_LOCK(priv);
1269 opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1270
1271 sbuf_printf(&sb, "pages irq %d\n",
1272 priv->mdev->priv.msix_arr[MLX5_EQ_VEC_PAGES].vector);
1273 sbuf_printf(&sb, "command irq %d\n",
1274 priv->mdev->priv.msix_arr[MLX5_EQ_VEC_CMD].vector);
1275 sbuf_printf(&sb, "async irq %d\n",
1276 priv->mdev->priv.msix_arr[MLX5_EQ_VEC_ASYNC].vector);
1277
1278 for (i = 0; i != priv->params.num_channels; i++) {
1279 int eqn_not_used = -1;
1280 int irqn = MLX5_EQ_VEC_COMP_BASE;
1281
1282 if (mlx5_vector2eqn(priv->mdev, i, &eqn_not_used, &irqn) != 0)
1283 continue;
1284
1285 c = opened ? &priv->channel[i] : NULL;
1286 rq = opened ? &c->rq : NULL;
1287 sbuf_printf(&sb, "channel %d rq %d cq %d irq %d\n", i,
1288 opened ? rq->rqn : -1,
1289 opened ? rq->cq.mcq.cqn : -1,
1290 priv->mdev->priv.msix_arr[irqn].vector);
1291
1292 for (tc = 0; tc != priv->num_tc; tc++) {
1293 sq = opened ? &c->sq[tc] : NULL;
1294 sbuf_printf(&sb, "channel %d tc %d sq %d cq %d irq %d\n",
1295 i, tc,
1296 opened ? sq->sqn : -1,
1297 opened ? sq->cq.mcq.cqn : -1,
1298 priv->mdev->priv.msix_arr[irqn].vector);
1299 }
1300 }
1301 PRIV_UNLOCK(priv);
1302 error = sbuf_finish(&sb);
1303 sbuf_delete(&sb);
1304 return (error);
1305 }
1306
1307 static int
mlx5e_ethtool_debug_stats(SYSCTL_HANDLER_ARGS)1308 mlx5e_ethtool_debug_stats(SYSCTL_HANDLER_ARGS)
1309 {
1310 struct mlx5e_priv *priv = arg1;
1311 int sys_debug;
1312 int error;
1313
1314 PRIV_LOCK(priv);
1315 if (priv->gone != 0) {
1316 error = ENODEV;
1317 goto done;
1318 }
1319 sys_debug = priv->sysctl_debug;
1320 error = sysctl_handle_int(oidp, &sys_debug, 0, req);
1321 if (error != 0 || !req->newptr)
1322 goto done;
1323 sys_debug = sys_debug ? 1 : 0;
1324 if (sys_debug == priv->sysctl_debug)
1325 goto done;
1326
1327 if ((priv->sysctl_debug = sys_debug)) {
1328 mlx5e_create_stats(&priv->stats.port_stats_debug.ctx,
1329 SYSCTL_CHILDREN(priv->sysctl_ifnet), "debug_stats",
1330 mlx5e_port_stats_debug_desc, MLX5E_PORT_STATS_DEBUG_NUM,
1331 priv->stats.port_stats_debug.arg);
1332 SYSCTL_ADD_PROC(&priv->stats.port_stats_debug.ctx,
1333 SYSCTL_CHILDREN(priv->sysctl_ifnet), OID_AUTO,
1334 "hw_ctx_debug",
1335 CTLFLAG_RD | CTLFLAG_MPSAFE | CTLTYPE_STRING, priv, 0,
1336 mlx5e_ethtool_debug_channel_info, "S", "");
1337 } else {
1338 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
1339 }
1340 done:
1341 PRIV_UNLOCK(priv);
1342 return (error);
1343 }
1344
1345 static void
mlx5e_create_diagnostics(struct mlx5e_priv * priv)1346 mlx5e_create_diagnostics(struct mlx5e_priv *priv)
1347 {
1348 struct mlx5_core_diagnostics_entry entry;
1349 struct sysctl_ctx_list *ctx;
1350 struct sysctl_oid *node;
1351 int x;
1352
1353 /* sysctl context we are using */
1354 ctx = &priv->sysctl_ctx;
1355
1356 /* create root node */
1357 node = SYSCTL_ADD_NODE(ctx,
1358 SYSCTL_CHILDREN(priv->sysctl_ifnet), OID_AUTO,
1359 "diagnostics", CTLFLAG_RD, NULL, "Diagnostics");
1360 if (node == NULL)
1361 return;
1362
1363 /* create PCI diagnostics */
1364 for (x = 0; x != MLX5_CORE_PCI_DIAGNOSTICS_NUM; x++) {
1365 entry = mlx5_core_pci_diagnostics_table[x];
1366 if (mlx5_core_supports_diagnostics(priv->mdev, entry.counter_id) == 0)
1367 continue;
1368 SYSCTL_ADD_UQUAD(ctx, SYSCTL_CHILDREN(node), OID_AUTO,
1369 entry.desc, CTLFLAG_RD, priv->params_pci.array + x,
1370 "PCI diagnostics counter");
1371 }
1372
1373 /* create general diagnostics */
1374 for (x = 0; x != MLX5_CORE_GENERAL_DIAGNOSTICS_NUM; x++) {
1375 entry = mlx5_core_general_diagnostics_table[x];
1376 if (mlx5_core_supports_diagnostics(priv->mdev, entry.counter_id) == 0)
1377 continue;
1378 SYSCTL_ADD_UQUAD(ctx, SYSCTL_CHILDREN(node), OID_AUTO,
1379 entry.desc, CTLFLAG_RD, priv->params_general.array + x,
1380 "General diagnostics counter");
1381 }
1382 }
1383
1384 void
mlx5e_create_ethtool(struct mlx5e_priv * priv)1385 mlx5e_create_ethtool(struct mlx5e_priv *priv)
1386 {
1387 struct sysctl_oid *fec_node;
1388 struct sysctl_oid *qos_node;
1389 struct sysctl_oid *node;
1390 const char *pnameunit;
1391 struct mlx5e_port_buffer port_buffer;
1392 unsigned x;
1393 int i;
1394
1395 /* set some defaults */
1396 priv->params_ethtool.tx_queue_size_max = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
1397 priv->params_ethtool.rx_queue_size_max = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
1398 priv->params_ethtool.tx_queue_size = 1 << priv->params.log_sq_size;
1399 priv->params_ethtool.rx_queue_size = 1 << priv->params.log_rq_size;
1400 priv->params_ethtool.channels = priv->params.num_channels;
1401 priv->params_ethtool.channels_rsss = priv->params.channels_rsss;
1402 priv->params_ethtool.coalesce_pkts_max = MLX5E_FLD_MAX(cqc, cq_max_count);
1403 priv->params_ethtool.coalesce_usecs_max = MLX5E_FLD_MAX(cqc, cq_period);
1404 priv->params_ethtool.rx_coalesce_mode = priv->params.rx_cq_moderation_mode;
1405 priv->params_ethtool.rx_coalesce_usecs = priv->params.rx_cq_moderation_usec;
1406 priv->params_ethtool.rx_coalesce_pkts = priv->params.rx_cq_moderation_pkts;
1407 priv->params_ethtool.tx_coalesce_mode = priv->params.tx_cq_moderation_mode;
1408 priv->params_ethtool.tx_coalesce_usecs = priv->params.tx_cq_moderation_usec;
1409 priv->params_ethtool.tx_coalesce_pkts = priv->params.tx_cq_moderation_pkts;
1410 priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
1411 priv->params_ethtool.cqe_zipping = priv->params.cqe_zipping_en;
1412 mlx5e_ethtool_sync_tx_completion_fact(priv);
1413
1414 /* get default values for local loopback, if any */
1415 if (MLX5_CAP_GEN(priv->mdev, disable_local_lb)) {
1416 int err;
1417 u8 val;
1418
1419 err = mlx5_nic_vport_query_local_lb(priv->mdev, MLX5_LOCAL_MC_LB, &val);
1420 if (err == 0)
1421 priv->params_ethtool.mc_local_lb = val;
1422
1423 err = mlx5_nic_vport_query_local_lb(priv->mdev, MLX5_LOCAL_UC_LB, &val);
1424 if (err == 0)
1425 priv->params_ethtool.uc_local_lb = val;
1426 }
1427
1428 /* create root node */
1429 node = SYSCTL_ADD_NODE(&priv->sysctl_ctx,
1430 SYSCTL_CHILDREN(priv->sysctl_ifnet), OID_AUTO,
1431 "conf", CTLFLAG_RW, NULL, "Configuration");
1432 if (node == NULL)
1433 return;
1434 for (x = 0; x != MLX5E_PARAMS_NUM; x++) {
1435 /* check for read-only parameter */
1436 if (strstr(mlx5e_params_desc[2 * x], "_max") != NULL ||
1437 strstr(mlx5e_params_desc[2 * x], "_mtu") != NULL) {
1438 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(node), OID_AUTO,
1439 mlx5e_params_desc[2 * x], CTLTYPE_U64 | CTLFLAG_RD |
1440 CTLFLAG_MPSAFE, priv, x, &mlx5e_ethtool_handler, "QU",
1441 mlx5e_params_desc[2 * x + 1]);
1442 } else {
1443 #if (__FreeBSD_version < 1100000)
1444 char path[64];
1445 #endif
1446 /*
1447 * NOTE: In FreeBSD-11 and newer the
1448 * CTLFLAG_RWTUN flag will take care of
1449 * loading default sysctl value from the
1450 * kernel environment, if any:
1451 */
1452 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(node), OID_AUTO,
1453 mlx5e_params_desc[2 * x], CTLTYPE_U64 | CTLFLAG_RWTUN |
1454 CTLFLAG_MPSAFE, priv, x, &mlx5e_ethtool_handler, "QU",
1455 mlx5e_params_desc[2 * x + 1]);
1456
1457 #if (__FreeBSD_version < 1100000)
1458 /* compute path for sysctl */
1459 snprintf(path, sizeof(path), "dev.mce.%d.conf.%s",
1460 device_get_unit(priv->mdev->pdev->dev.bsddev),
1461 mlx5e_params_desc[2 * x]);
1462
1463 /* try to fetch tunable, if any */
1464 if (TUNABLE_QUAD_FETCH(path, &priv->params_ethtool.arg[x]))
1465 mlx5e_ethtool_handler(NULL, priv, x, NULL);
1466 #endif
1467 }
1468 }
1469
1470 /* create fec node */
1471 fec_node = SYSCTL_ADD_NODE(&priv->sysctl_ctx,
1472 SYSCTL_CHILDREN(node), OID_AUTO,
1473 "fec", CTLFLAG_RW, NULL, "Forward Error Correction");
1474 if (fec_node == NULL)
1475 return;
1476
1477 if (mlx5e_fec_update(priv) == 0) {
1478 SYSCTL_ADD_U32(&priv->sysctl_ctx, SYSCTL_CHILDREN(fec_node), OID_AUTO,
1479 "mode_active", CTLFLAG_RD | CTLFLAG_MPSAFE,
1480 &priv->params_ethtool.fec_mode_active, 0,
1481 "Current FEC mode bit, if any.");
1482
1483 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(fec_node), OID_AUTO,
1484 "mask_10x_25x", CTLTYPE_U8 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1485 priv, 0, &mlx5e_fec_mask_10x_25x_handler, "CU",
1486 "Set FEC masks for 10G_40G, 25G_50G, 56G, 100G respectivly. "
1487 "0:Auto "
1488 "1:NOFEC "
1489 "2:FIRECODE "
1490 "4:RS");
1491
1492 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(fec_node), OID_AUTO,
1493 "avail_10x_25x", CTLTYPE_U8 | CTLFLAG_RD | CTLFLAG_MPSAFE,
1494 priv, 0, &mlx5e_fec_avail_10x_25x_handler, "CU",
1495 "Get available FEC bits for 10G_40G, 25G_50G, 56G, 100G respectivly. "
1496 "0:Auto "
1497 "1:NOFEC "
1498 "2:FIRECODE "
1499 "4:RS");
1500
1501 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(fec_node), OID_AUTO,
1502 "mask_50x", CTLTYPE_U16 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1503 priv, 0, &mlx5e_fec_mask_50x_handler, "SU",
1504 "Set FEC masks for 50G 1x, 100G 2x, 200G 4x, 400G 8x respectivly. "
1505 "0:Auto "
1506 "128:RS "
1507 "512:LL RS");
1508
1509 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(fec_node), OID_AUTO,
1510 "avail_50x", CTLTYPE_U16 | CTLFLAG_RD | CTLFLAG_MPSAFE,
1511 priv, 0, &mlx5e_fec_avail_50x_handler, "SU",
1512 "Get available FEC bits for 50G 1x, 100G 2x, 200G 4x, 400G 8x respectivly. "
1513 "0:Auto "
1514 "128:RS "
1515 "512:LL RS");
1516 }
1517
1518 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(node), OID_AUTO,
1519 "debug_stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, priv,
1520 0, &mlx5e_ethtool_debug_stats, "I", "Extended debug statistics");
1521
1522 pnameunit = device_get_nameunit(priv->mdev->pdev->dev.bsddev);
1523
1524 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(node),
1525 OID_AUTO, "device_name", CTLFLAG_RD,
1526 __DECONST(void *, pnameunit), 0,
1527 "PCI device name");
1528
1529 /* Diagnostics support */
1530 mlx5e_create_diagnostics(priv);
1531
1532 /* create qos node */
1533 qos_node = SYSCTL_ADD_NODE(&priv->sysctl_ctx,
1534 SYSCTL_CHILDREN(node), OID_AUTO,
1535 "qos", CTLFLAG_RW, NULL, "Quality Of Service configuration");
1536 if (qos_node == NULL)
1537 return;
1538
1539 /* Priority rate limit support */
1540 if (mlx5e_getmaxrate(priv) == 0) {
1541 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
1542 OID_AUTO, "tc_max_rate", CTLTYPE_U64 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1543 priv, 0, mlx5e_tc_maxrate_handler, "QU",
1544 "Max rate for priority, specified in kilobits, where kilo=1000, "
1545 "max_rate must be divisible by 100000");
1546 }
1547
1548 /* Bandwidth limiting by ratio */
1549 if (mlx5e_get_max_alloc(priv) == 0) {
1550 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
1551 OID_AUTO, "tc_rate_share", CTLTYPE_U8 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1552 priv, 0, mlx5e_tc_rate_share_handler, "QU",
1553 "Specify bandwidth ratio from 1 to 100 "
1554 "for the available traffic classes");
1555 }
1556
1557 /* Priority to traffic class mapping */
1558 if (mlx5e_get_prio_tc(priv) == 0) {
1559 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
1560 OID_AUTO, "prio_0_7_tc", CTLTYPE_U8 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1561 priv, 0, mlx5e_prio_to_tc_handler, "CU",
1562 "Set traffic class 0 to 7 for priority 0 to 7 inclusivly");
1563 }
1564
1565 /* DSCP support */
1566 if (mlx5e_get_dscp(priv) == 0) {
1567 for (i = 0; i != MLX5_MAX_SUPPORTED_DSCP; i += 8) {
1568 char name[32];
1569 snprintf(name, sizeof(name), "dscp_%d_%d_prio", i, i + 7);
1570 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
1571 OID_AUTO, name, CTLTYPE_U8 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1572 priv, i, mlx5e_dscp_prio_handler, "CU",
1573 "Set DSCP to priority mapping, 0..7");
1574 }
1575 #define A "Set trust state, 1:PCP 2:DSCP"
1576 #define B " 3:BOTH"
1577 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
1578 OID_AUTO, "trust_state", CTLTYPE_U8 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1579 priv, 0, mlx5e_trust_state_handler, "CU",
1580 MLX5_CAP_QCAM_FEATURE(priv->mdev, qpts_trust_both) ?
1581 A B : A);
1582 #undef B
1583 #undef A
1584 }
1585
1586 if (mlx5e_port_query_buffer(priv, &port_buffer) == 0) {
1587 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
1588 OID_AUTO, "buffers_size",
1589 CTLTYPE_U32 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1590 priv, 0, mlx5e_buf_size_handler, "IU",
1591 "Set buffers sizes");
1592 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
1593 OID_AUTO, "buffers_prio",
1594 CTLTYPE_U8 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1595 priv, 0, mlx5e_buf_prio_handler, "CU",
1596 "Set prio to buffers mapping");
1597 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
1598 OID_AUTO, "cable_length",
1599 CTLTYPE_UINT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1600 priv, 0, mlx5e_cable_length_handler, "IU",
1601 "Set cable length in meters for xoff threshold calculation");
1602 }
1603
1604 if (mlx5e_hw_temperature_update(priv) == 0) {
1605 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1606 OID_AUTO, "hw_temperature",
1607 CTLTYPE_S32 | CTLFLAG_RD | CTLFLAG_MPSAFE,
1608 priv, 0, mlx5e_hw_temperature_handler, "I",
1609 "HW temperature in millicelsius");
1610 }
1611 }
1612