1 /* $NetBSD: if_gfevar.h,v 1.13 2015/04/14 20:32:36 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 #ifndef _IF_GFEVAR_H_ 40 #define _IF_GFEVAR_H_ 41 42 #include <sys/rndsource.h> 43 44 #define GE_RXDESC_MEMSIZE (1 * PAGE_SIZE) 45 #define GE_RXDESC_MAX 64 46 #define GE_RXBUF_SIZE 2048 47 #define GE_RXBUF_MEMSIZE (GE_RXDESC_MAX*GE_RXBUF_SIZE) 48 #define GE_RXBUF_NSEGS ((GE_RXBUF_MEMSIZE/PAGE_SIZE)+1) 49 #define GE_DMSEG_MAX (GE_RXBUF_NSEGS) 50 51 struct gfe_dmamem { 52 bus_dmamap_t gdm_map; /* dmamem'ed memory */ 53 void *gdm_kva; /* kva of tx memory */ 54 int gdm_nsegs; /* # of segment in gdm_segs */ 55 int gdm_maxsegs; /* maximum # of segments allowed */ 56 size_t gdm_size; /* size of memory region */ 57 bus_dma_segment_t gdm_segs[GE_DMSEG_MAX]; /* dma segment of tx memory */ 58 }; 59 60 /* With a 4096 page size, we get 256 descriptors per page. 61 */ 62 #define GE_TXDESC_MEMSIZE (1 * PAGE_SIZE) 63 #define GE_TXDESC_MAX (GE_TXDESC_MEMSIZE / 16) 64 #define GE_TXBUF_SIZE (4 * PAGE_SIZE) 65 66 struct gfe_txqueue { 67 struct ifqueue txq_pendq; /* these are ready to go to the GT */ 68 struct gfe_dmamem txq_desc_mem; /* transmit descriptor memory */ 69 struct gfe_dmamem txq_buf_mem; /* transmit buffer memory */ 70 unsigned int txq_lo; /* next to be given to GT */ 71 unsigned int txq_fi; /* next to be returned to CPU */ 72 unsigned int txq_ei_gapcount; /* counter until next EI */ 73 unsigned int txq_nactive; /* number of active descriptors */ 74 unsigned int txq_outptr; /* where to put next transmit packet */ 75 unsigned int txq_inptr; /* start of 1st queued tx packet */ 76 uint32_t txq_intrbits; /* bits to write to EIMR */ 77 uint32_t txq_esdcmrbits; /* bits to write to ESDCMR */ 78 uint32_t txq_epsrbits; /* bits to test with EPSR */ 79 volatile struct gt_eth_desc *txq_descs; /* ptr to tx descriptors */ 80 bus_addr_t txq_ectdp; /* offset to cur. tx desc ptr reg */ 81 bus_addr_t txq_desc_busaddr; /* bus addr of tx descriptors */ 82 bus_addr_t txq_buf_busaddr; /* bus addr of tx buffers */ 83 }; 84 85 /* With a 4096 page size, we get 256 descriptors per page. We want 1024 86 * which will give us about 8ms of 64 byte packets (2ms for each priority 87 * queue). 88 */ 89 90 struct gfe_rxbuf { 91 uint8_t rxb_data[GE_RXBUF_SIZE]; 92 }; 93 94 struct gfe_rxqueue { 95 struct gfe_dmamem rxq_desc_mem; /* receive descriptor memory */ 96 struct gfe_dmamem rxq_buf_mem; /* receive buffer memory */ 97 struct mbuf *rxq_curpkt; /* mbuf for current packet */ 98 volatile struct gt_eth_desc *rxq_descs; 99 struct gfe_rxbuf *rxq_bufs; 100 unsigned int rxq_fi; /* next to be returned to CPU */ 101 unsigned int rxq_active; /* # of descriptors given to GT */ 102 uint32_t rxq_intrbits; /* bits to write to EIMR */ 103 bus_addr_t rxq_desc_busaddr; /* bus addr of rx descriptors */ 104 uint32_t rxq_cmdsts; /* save cmdsts from first descriptor */ 105 bus_size_t rxq_efrdp; 106 bus_size_t rxq_ecrdp; 107 }; 108 109 enum gfe_txprio { 110 GE_TXPRIO_HI=1, 111 GE_TXPRIO_LO=0, 112 GE_TXPRIO_NONE=2 113 }; 114 enum gfe_rxprio { 115 GE_RXPRIO_HI=3, 116 GE_RXPRIO_MEDHI=2, 117 GE_RXPRIO_MEDLO=1, 118 GE_RXPRIO_LO=0 119 }; 120 121 struct gfec_softc { 122 device_t sc_dev; /* must be first */ 123 124 bus_space_tag_t sc_iot; 125 bus_space_handle_t sc_ioh; /* subregion for ethernet */ 126 127 kmutex_t sc_mtx; 128 }; 129 130 struct gfe_softc { 131 device_t sc_dev; /* must be first */ 132 struct ethercom sc_ec; /* common ethernet glue */ 133 struct callout sc_co; /* resource recovery */ 134 mii_data_t sc_mii; /* mii interface */ 135 136 bus_space_tag_t sc_memt; 137 bus_space_handle_t sc_memh; /* subregion for ethernet */ 138 bus_dma_tag_t sc_dmat; 139 int sc_macno; /* which mac? 0, 1, or 2 */ 140 141 unsigned int sc_tickflags; 142 #define GE_TICK_TX_IFSTART 0x0001 143 #define GE_TICK_RX_RESTART 0x0002 144 unsigned int sc_flags; 145 #define GE_ALLMULTI 0x0001 146 #define GE_PHYSTSCHG 0x0002 147 #define GE_RXACTIVE 0x0004 148 #define GE_NOFREE 0x0008 /* Don't free on disable */ 149 uint32_t sc_pcr; /* current EPCR value */ 150 uint32_t sc_pcxr; /* current EPCXR value */ 151 uint32_t sc_intrmask; /* current EIMR value */ 152 uint32_t sc_idlemask; /* suspended EIMR bits */ 153 size_t sc_max_frame_length; /* maximum frame length */ 154 155 /* 156 * Hash table related members 157 */ 158 struct gfe_dmamem sc_hash_mem; /* dma'ble hash table */ 159 uint64_t *sc_hashtable; 160 unsigned int sc_hashmask; /* 0x1ff or 0x1fff */ 161 162 /* 163 * Transmit related members 164 */ 165 struct gfe_txqueue sc_txq[2]; /* High & Low transmit queues */ 166 167 /* 168 * Receive related members 169 */ 170 struct gfe_rxqueue sc_rxq[4]; /* Hi/MedHi/MedLo/Lo receive queues */ 171 172 krndsource_t sc_rnd_source; 173 }; 174 #endif /* _IF_GFEVAR_H_ */ 175