| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| HD | mmsch_v1_0.h | 51 uint32_t reg_offset : 28; member
56 uint32_t reg_offset : 20; member
89 uint32_t reg_offset, in mmsch_v1_0_insert_direct_wt()
99 uint32_t reg_offset, in mmsch_v1_0_insert_direct_rd_mod_wt()
111 uint32_t reg_offset, in mmsch_v1_0_insert_direct_poll()
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| HD | soc15.c | 270 uint32_t reg_offset; member
298 u32 sh_num, u32 reg_offset) in soc15_read_indexed_register()
316 u32 sh_num, u32 reg_offset) in soc15_get_register_value()
330 u32 sh_num, u32 reg_offset, u32 *value) in soc15_read_register()
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| HD | vcn_v1_0.c | 1405 uint32_t reg_offset = (reg << 2); in vcn_v1_0_jpeg_ring_emit_reg_wait() local
1449 uint32_t reg_offset = (reg << 2); in vcn_v1_0_jpeg_ring_emit_wreg() local
1478 …v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t v… in vcn_v1_0_jpeg_ring_patch_wreg()
1497 uint32_t reg, reg_offset, val, mask, i; in vcn_v1_0_jpeg_ring_set_patch_ring() local
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| HD | cik.c | 1028 u32 sh_num, u32 reg_offset) in cik_get_register_value()
1123 u32 sh_num, u32 reg_offset, u32 *value) in cik_read_register()
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| HD | vi.c | 552 u32 sh_num, u32 reg_offset) in vi_get_register_value()
647 u32 sh_num, u32 reg_offset, u32 *value) in vi_read_register()
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| HD | amdgpu_amdkfd_gfx_v8.c | 763 unsigned int reg_offset) in kgd_address_watch_get_offset()
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| HD | amdgpu_amdkfd_gfx_v9.c | 949 unsigned int reg_offset) in kgd_address_watch_get_offset()
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| HD | sdma_v4_0.c | 1378 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ? in sdma_v4_0_set_trap_irq_state() local
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| HD | amdgpu.h | 1137 uint32_t reg_offset; member
1543 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; member
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| HD | gfx_v8_0.c | 2231 u32 reg_offset; in gfx_v8_0_tiling_mode_table_init() local
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| HD | si_dpm.c | 3653 u16 reg_offset, u32 value) in si_write_smc_soft_register()
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| /dragonfly/sys/dev/drm/radeon/ |
| HD | cik_sdma.c | 250 u32 rb_cntl, reg_offset; in cik_sdma_gfx_stop() local
304 uint32_t reg_offset, value; in cik_sdma_ctx_switch_enable() local
331 u32 me_cntl, reg_offset; in cik_sdma_enable() local
368 u32 reg_offset, wb_offset; in cik_sdma_gfx_resume() local
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| HD | ni_dma.c | 190 u32 reg_offset, wb_offset; in cayman_dma_resume() local
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| HD | rv770_dpm.c | 251 u16 reg_offset, u32 value) in rv770_write_smc_soft_register()
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| HD | si.c | 2484 u32 reg_offset, split_equal_to_row_size; in si_tiling_mode_table_init() local
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| HD | cik.c | 2356 u32 reg_offset, split_equal_to_row_size; in cik_tiling_mode_table_init() local
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| HD | ci_dpm.c | 1327 u16 reg_offset, u32 value) in ci_write_smc_soft_register()
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| HD | si_dpm.c | 3194 u16 reg_offset, u32 value) in si_write_smc_soft_register()
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| /dragonfly/contrib/gdb-7/gdb/ |
| HD | amd64-nat.c | 57 int *reg_offset = amd64_native_gregset64_reg_offset; in amd64_native_gregset_reg_offset() local
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| HD | findvar.c | 687 int reg_offset = value_offset (value); in read_frame_register_value() local
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| HD | dwarf2loc.c | 1629 int reg_offset = source_offset; in read_pieced_value() local
1821 int reg_offset = dest_offset; in write_pieced_value() local
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| /dragonfly/sys/dev/netif/ix/ |
| HD | ixgbe_mbx.c | 597 u32 reg_offset = (vf_number < 32) ? 0 : 1; in ixgbe_check_for_rst_pf() local
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| /dragonfly/contrib/gcc-4.7/gcc/ |
| HD | postreload.c | 1640 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; variable
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| /dragonfly/contrib/gcc-8.0/gcc/ |
| HD | postreload.c | 1631 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; variable
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| /dragonfly/sys/dev/netif/ig_hal/ |
| HD | e1000_82575.c | 2276 u32 reg_val, reg_offset; in e1000_vmdq_set_anti_spoofing_pf() local
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