1 /* $NetBSD: pci_swiz_bus_mem_chipdep.c,v 1.50 2025/01/07 20:14:52 andvar Exp $ */
2
3 /*-
4 * Copyright (c) 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Copyright (c) 1995, 1996 Carnegie-Mellon University.
34 * All rights reserved.
35 *
36 * Author: Chris G. Demetriou
37 *
38 * Permission to use, copy, modify and distribute this software and
39 * its documentation is hereby granted, provided that both the copyright
40 * notice and this permission notice appear in all copies of the
41 * software, derivative works or modified versions, and any portions
42 * thereof, and that both notices appear in supporting documentation.
43 *
44 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
45 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
46 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
47 *
48 * Carnegie Mellon requests users of this software to return to
49 *
50 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
51 * School of Computer Science
52 * Carnegie Mellon University
53 * Pittsburgh PA 15213-3890
54 *
55 * any improvements or extensions that they make and grant Carnegie the
56 * rights to redistribute these changes.
57 */
58
59 /*
60 * Common PCI Chipset "bus I/O" functions, for chipsets which have to
61 * deal with only a single PCI interface chip in a machine.
62 *
63 * uses:
64 * CHIP name of the 'chip' it's being compiled for.
65 * CHIP_D_MEM_W1_SYS_START Dense Mem space base to use.
66 * CHIP_D_MEM_ARENA_STORE
67 * If defined, device-provided static storage area
68 * for the dense memory space arena. If this is
69 * defined, CHIP_D_MEM_BTAG_STORE and
70 * CHIP_D_MEM_BTAG_COUNT must also be defined. If
71 * this is not defined, a static area will be declared.
72 * CHIP_D_MEM_BTAG_STORE
73 * Device-provided static storage area for the
74 * dense memory space arena's boundary tags. Ignored
75 * unless CHIP_D_MEM_ARENA_STORE is defined.
76 * CHIP_D_MEM_BTAG_COUNT
77 * The number of device-provided static dense memory
78 * space boundary tags. Ignored unless
79 * CHIP_MEM_ARENA_STORE is defined.
80 * CHIP_S_MEM_BASE Sparse Mem space base to use.
81 * CHIP_S_MEM_ARENA_STORE
82 * If defined, device-provided static storage area
83 * for the sparse memory space arena. If this is
84 * defined, CHIP_D_MEM_BTAG_STORE and
85 * CHIP_D_MEM_BTAG_COUNT must also be defined. If
86 * this is not defined, a static area will be declared.
87 * CHIP_S_MEM_BTAG_STORE
88 * Device-provided static storage area for the
89 * sparse memory space arena's boundary tags. Ignored
90 * unless CHIP_D_MEM_ARENA_STORE is defined.
91 * CHIP_S_MEM_BTAG_COUNT
92 * The number of device-provided static sparse memory
93 * space boundary tags. Ignored unless
94 * CHIP_MEM_ARENA_STORE is defined.
95 */
96
97 #include <sys/cdefs.h>
98 __KERNEL_RCSID(1, "$NetBSD: pci_swiz_bus_mem_chipdep.c,v 1.50 2025/01/07 20:14:52 andvar Exp $");
99
100 #include <sys/vmem_impl.h>
101
102 #define __C(A,B) __CONCAT(A,B)
103 #define __S(S) __STRING(S)
104
105 /* mapping/unmapping */
106 static int __C(CHIP,_mem_map)(void *, bus_addr_t, bus_size_t, int,
107 bus_space_handle_t *, int);
108 static void __C(CHIP,_mem_unmap)(void *, bus_space_handle_t,
109 bus_size_t, int);
110 static int __C(CHIP,_mem_subregion)(void *, bus_space_handle_t,
111 bus_size_t, bus_size_t, bus_space_handle_t *);
112
113 static int __C(CHIP,_mem_translate)(void *, bus_addr_t, bus_size_t,
114 int, struct alpha_bus_space_translation *);
115 static int __C(CHIP,_mem_get_window)(void *, int,
116 struct alpha_bus_space_translation *);
117
118 /* allocation/deallocation */
119 static int __C(CHIP,_mem_alloc)(void *, bus_addr_t, bus_addr_t,
120 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *,
121 bus_space_handle_t *);
122 static void __C(CHIP,_mem_free)(void *, bus_space_handle_t,
123 bus_size_t);
124
125 /* get kernel virtual address */
126 static void * __C(CHIP,_mem_vaddr)(void *, bus_space_handle_t);
127
128 /* mmap for user */
129 static paddr_t __C(CHIP,_mem_mmap)(void *, bus_addr_t, off_t, int, int);
130
131 /* barrier */
132 static inline void __C(CHIP,_mem_barrier)(void *, bus_space_handle_t,
133 bus_size_t, bus_size_t, int);
134
135 /* read (single) */
136 static inline uint8_t __C(CHIP,_mem_read_1)(void *, bus_space_handle_t,
137 bus_size_t);
138 static inline uint16_t __C(CHIP,_mem_read_2)(void *, bus_space_handle_t,
139 bus_size_t);
140 static inline uint32_t __C(CHIP,_mem_read_4)(void *, bus_space_handle_t,
141 bus_size_t);
142 static inline uint64_t __C(CHIP,_mem_read_8)(void *, bus_space_handle_t,
143 bus_size_t);
144
145 /* read multiple */
146 static void __C(CHIP,_mem_read_multi_1)(void *, bus_space_handle_t,
147 bus_size_t, uint8_t *, bus_size_t);
148 static void __C(CHIP,_mem_read_multi_2)(void *, bus_space_handle_t,
149 bus_size_t, uint16_t *, bus_size_t);
150 static void __C(CHIP,_mem_read_multi_4)(void *, bus_space_handle_t,
151 bus_size_t, uint32_t *, bus_size_t);
152 static void __C(CHIP,_mem_read_multi_8)(void *, bus_space_handle_t,
153 bus_size_t, uint64_t *, bus_size_t);
154
155 /* read region */
156 static void __C(CHIP,_mem_read_region_1)(void *, bus_space_handle_t,
157 bus_size_t, uint8_t *, bus_size_t);
158 static void __C(CHIP,_mem_read_region_2)(void *, bus_space_handle_t,
159 bus_size_t, uint16_t *, bus_size_t);
160 static void __C(CHIP,_mem_read_region_4)(void *, bus_space_handle_t,
161 bus_size_t, uint32_t *, bus_size_t);
162 static void __C(CHIP,_mem_read_region_8)(void *, bus_space_handle_t,
163 bus_size_t, uint64_t *, bus_size_t);
164
165 /* write (single) */
166 static inline void __C(CHIP,_mem_write_1)(void *, bus_space_handle_t,
167 bus_size_t, uint8_t);
168 static inline void __C(CHIP,_mem_write_2)(void *, bus_space_handle_t,
169 bus_size_t, uint16_t);
170 static inline void __C(CHIP,_mem_write_4)(void *, bus_space_handle_t,
171 bus_size_t, uint32_t);
172 static inline void __C(CHIP,_mem_write_8)(void *, bus_space_handle_t,
173 bus_size_t, uint64_t);
174
175 /* write multiple */
176 static void __C(CHIP,_mem_write_multi_1)(void *, bus_space_handle_t,
177 bus_size_t, const uint8_t *, bus_size_t);
178 static void __C(CHIP,_mem_write_multi_2)(void *, bus_space_handle_t,
179 bus_size_t, const uint16_t *, bus_size_t);
180 static void __C(CHIP,_mem_write_multi_4)(void *, bus_space_handle_t,
181 bus_size_t, const uint32_t *, bus_size_t);
182 static void __C(CHIP,_mem_write_multi_8)(void *, bus_space_handle_t,
183 bus_size_t, const uint64_t *, bus_size_t);
184
185 /* write region */
186 static void __C(CHIP,_mem_write_region_1)(void *, bus_space_handle_t,
187 bus_size_t, const uint8_t *, bus_size_t);
188 static void __C(CHIP,_mem_write_region_2)(void *, bus_space_handle_t,
189 bus_size_t, const uint16_t *, bus_size_t);
190 static void __C(CHIP,_mem_write_region_4)(void *, bus_space_handle_t,
191 bus_size_t, const uint32_t *, bus_size_t);
192 static void __C(CHIP,_mem_write_region_8)(void *, bus_space_handle_t,
193 bus_size_t, const uint64_t *, bus_size_t);
194
195 /* set multiple */
196 static void __C(CHIP,_mem_set_multi_1)(void *, bus_space_handle_t,
197 bus_size_t, uint8_t, bus_size_t);
198 static void __C(CHIP,_mem_set_multi_2)(void *, bus_space_handle_t,
199 bus_size_t, uint16_t, bus_size_t);
200 static void __C(CHIP,_mem_set_multi_4)(void *, bus_space_handle_t,
201 bus_size_t, uint32_t, bus_size_t);
202 static void __C(CHIP,_mem_set_multi_8)(void *, bus_space_handle_t,
203 bus_size_t, uint64_t, bus_size_t);
204
205 /* set region */
206 static void __C(CHIP,_mem_set_region_1)(void *, bus_space_handle_t,
207 bus_size_t, uint8_t, bus_size_t);
208 static void __C(CHIP,_mem_set_region_2)(void *, bus_space_handle_t,
209 bus_size_t, uint16_t, bus_size_t);
210 static void __C(CHIP,_mem_set_region_4)(void *, bus_space_handle_t,
211 bus_size_t, uint32_t, bus_size_t);
212 static void __C(CHIP,_mem_set_region_8)(void *, bus_space_handle_t,
213 bus_size_t, uint64_t, bus_size_t);
214
215 /* copy */
216 static void __C(CHIP,_mem_copy_region_1)(void *, bus_space_handle_t,
217 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
218 static void __C(CHIP,_mem_copy_region_2)(void *, bus_space_handle_t,
219 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
220 static void __C(CHIP,_mem_copy_region_4)(void *, bus_space_handle_t,
221 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
222 static void __C(CHIP,_mem_copy_region_8)(void *, bus_space_handle_t,
223 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
224
225 #ifdef CHIP_D_MEM_W1_SYS_START
226 #ifndef CHIP_D_MEM_ARENA_STORE
227 #define CHIP_D_MEM_BTAG_COUNT(v) VMEM_EST_BTCOUNT(1, 8)
228 #define CHIP_D_MEM_BTAG_STORE(v) __C(CHIP,_dmem_btag_store)
229 #define CHIP_D_MEM_ARENA_STORE(v) (&(__C(CHIP,_dmem_arena_store)))
230
231 static struct vmem __C(CHIP,_dmem_arena_store);
232 static struct vmem_btag __C(CHIP,_dmem_btag_store)[CHIP_D_MEM_BTAG_COUNT(xxx)];
233 #endif /* CHIP_D_MEM_ARENA_STORE */
234 #endif /* CHIP_D_MEM_W1_SYS_START */
235
236 #ifndef CHIP_S_MEM_ARENA_STORE
237
238 #ifdef CHIP_S_MEM_W1_BUS_START
239 #define CHIP_S_MEM_W1_BUS_SPAN 1
240 #else
241 #define CHIP_S_MEM_W1_BUS_SPAN 0
242 #endif /* CHIP_S_MEM_W1_BUS_START */
243
244 #ifdef CHIP_S_MEM_W2_BUS_START
245 #define CHIP_S_MEM_W2_BUS_SPAN 1
246 #else
247 #define CHIP_S_MEM_W2_BUS_SPAN 0
248 #endif /* CHIP_S_MEM_W2_BUS_START */
249
250 #ifdef CHIP_S_MEM_W3_BUS_START
251 #define CHIP_S_MEM_W3_BUS_SPAN 1
252 #else
253 #define CHIP_S_MEM_W3_BUS_SPAN 0
254 #endif /* CHIP_S_MEM_W3_BUS_START */
255
256 #define CHIP_S_MEM_SPAN_COUNT \
257 (CHIP_S_MEM_W1_BUS_SPAN + CHIP_S_MEM_W2_BUS_SPAN + \
258 CHIP_S_MEM_W3_BUS_SPAN)
259
260 #define CHIP_S_MEM_BTAG_COUNT(v) VMEM_EST_BTCOUNT(CHIP_S_MEM_SPAN_COUNT, 8)
261 #define CHIP_S_MEM_BTAG_STORE(v) __C(CHIP,_smem_btag_store)
262 #define CHIP_S_MEM_ARENA_STORE(v) (&(__C(CHIP,_smem_arena_store)))
263
264 static struct vmem __C(CHIP,_smem_arena_store);
265 static struct vmem_btag __C(CHIP,_smem_btag_store)[CHIP_S_MEM_BTAG_COUNT(xxx)];
266
267 #endif /* CHIP_S_MEM_ARENA_STORE */
268
269 #ifndef CHIP_ADDR_SHIFT
270 #define CHIP_ADDR_SHIFT 5
271 #endif
272
273 #ifndef CHIP_SIZE_SHIFT
274 #define CHIP_SIZE_SHIFT 3
275 #endif
276
277 void
__C(CHIP,_bus_mem_init)278 __C(CHIP,_bus_mem_init)(bus_space_tag_t t, void *v)
279 {
280 #ifdef CHIP_D_MEM_W1_SYS_START
281 vmem_t *dvm;
282 #endif
283 vmem_t *svm;
284 int error __diagused;
285
286 /*
287 * Initialize the bus space tag.
288 */
289
290 /* cookie */
291 t->abs_cookie = v;
292
293 /* mapping/unmapping */
294 t->abs_map = __C(CHIP,_mem_map);
295 t->abs_unmap = __C(CHIP,_mem_unmap);
296 t->abs_subregion = __C(CHIP,_mem_subregion);
297
298 t->abs_translate = __C(CHIP,_mem_translate);
299 t->abs_get_window = __C(CHIP,_mem_get_window);
300
301 /* allocation/deallocation */
302 t->abs_alloc = __C(CHIP,_mem_alloc);
303 t->abs_free = __C(CHIP,_mem_free);
304
305 /* get kernel virtual address */
306 t->abs_vaddr = __C(CHIP,_mem_vaddr);
307
308 /* mmap for user */
309 t->abs_mmap = __C(CHIP,_mem_mmap);
310
311 /* barrier */
312 t->abs_barrier = __C(CHIP,_mem_barrier);
313
314 /* read (single) */
315 t->abs_r_1 = __C(CHIP,_mem_read_1);
316 t->abs_r_2 = __C(CHIP,_mem_read_2);
317 t->abs_r_4 = __C(CHIP,_mem_read_4);
318 t->abs_r_8 = __C(CHIP,_mem_read_8);
319
320 /* read multiple */
321 t->abs_rm_1 = __C(CHIP,_mem_read_multi_1);
322 t->abs_rm_2 = __C(CHIP,_mem_read_multi_2);
323 t->abs_rm_4 = __C(CHIP,_mem_read_multi_4);
324 t->abs_rm_8 = __C(CHIP,_mem_read_multi_8);
325
326 /* read region */
327 t->abs_rr_1 = __C(CHIP,_mem_read_region_1);
328 t->abs_rr_2 = __C(CHIP,_mem_read_region_2);
329 t->abs_rr_4 = __C(CHIP,_mem_read_region_4);
330 t->abs_rr_8 = __C(CHIP,_mem_read_region_8);
331
332 /* write (single) */
333 t->abs_w_1 = __C(CHIP,_mem_write_1);
334 t->abs_w_2 = __C(CHIP,_mem_write_2);
335 t->abs_w_4 = __C(CHIP,_mem_write_4);
336 t->abs_w_8 = __C(CHIP,_mem_write_8);
337
338 /* write multiple */
339 t->abs_wm_1 = __C(CHIP,_mem_write_multi_1);
340 t->abs_wm_2 = __C(CHIP,_mem_write_multi_2);
341 t->abs_wm_4 = __C(CHIP,_mem_write_multi_4);
342 t->abs_wm_8 = __C(CHIP,_mem_write_multi_8);
343
344 /* write region */
345 t->abs_wr_1 = __C(CHIP,_mem_write_region_1);
346 t->abs_wr_2 = __C(CHIP,_mem_write_region_2);
347 t->abs_wr_4 = __C(CHIP,_mem_write_region_4);
348 t->abs_wr_8 = __C(CHIP,_mem_write_region_8);
349
350 /* set multiple */
351 t->abs_sm_1 = __C(CHIP,_mem_set_multi_1);
352 t->abs_sm_2 = __C(CHIP,_mem_set_multi_2);
353 t->abs_sm_4 = __C(CHIP,_mem_set_multi_4);
354 t->abs_sm_8 = __C(CHIP,_mem_set_multi_8);
355
356 /* set region */
357 t->abs_sr_1 = __C(CHIP,_mem_set_region_1);
358 t->abs_sr_2 = __C(CHIP,_mem_set_region_2);
359 t->abs_sr_4 = __C(CHIP,_mem_set_region_4);
360 t->abs_sr_8 = __C(CHIP,_mem_set_region_8);
361
362 /* copy */
363 t->abs_c_1 = __C(CHIP,_mem_copy_region_1);
364 t->abs_c_2 = __C(CHIP,_mem_copy_region_2);
365 t->abs_c_4 = __C(CHIP,_mem_copy_region_4);
366 t->abs_c_8 = __C(CHIP,_mem_copy_region_8);
367
368 #ifdef CHIP_D_MEM_W1_SYS_START
369 dvm = vmem_init(CHIP_D_MEM_ARENA_STORE(v),
370 __S(__C(CHIP,_bus_dmem)), /* name */
371 0, /* addr */
372 0, /* size */
373 1, /* quantum */
374 NULL, /* importfn */
375 NULL, /* releasefn */
376 NULL, /* source */
377 0, /* qcache_max */
378 VM_NOSLEEP | VM_PRIVTAGS,
379 IPL_NONE);
380 KASSERT(dvm != NULL);
381
382 vmem_add_bts(dvm, CHIP_D_MEM_BTAG_STORE(v), CHIP_D_MEM_BTAG_COUNT(v));
383
384 #ifdef CHIP_D_MEM_W1_BUS_START
385 #ifdef EXTENT_DEBUG
386 printf("dmem: adding span 0x%lx to 0x%lx\n",
387 CHIP_D_MEM_W1_BUS_START(v), CHIP_D_MEM_W1_BUS_END(v));
388 #endif
389 error = vmem_add(dvm, CHIP_D_MEM_W1_BUS_START(v),
390 CHIP_D_MEM_W1_BUS_END(v) - CHIP_D_MEM_W1_BUS_START(v) + 1,
391 VM_NOSLEEP);
392 KASSERT(error == 0);
393 #endif /* CHIP_D_MEM_W1_BUS_START */
394
395 #ifdef EXTENT_DEBUG
396 /* vmem_print(dvm); XXX */
397 #endif
398 CHIP_D_MEM_ARENA(v) = dvm;
399 #endif /* CHIP_D_MEM_W1_SYS_START */
400
401 svm = vmem_init(CHIP_S_MEM_ARENA_STORE(v),
402 __S(__C(CHIP,_bus_smem)), /* name */
403 0, /* addr */
404 0, /* size */
405 1, /* quantum */
406 NULL, /* importfn */
407 NULL, /* releasefn */
408 NULL, /* source */
409 0, /* qcache_max */
410 VM_NOSLEEP | VM_PRIVTAGS,
411 IPL_NONE);
412 KASSERT(svm != NULL);
413
414 vmem_add_bts(svm, CHIP_S_MEM_BTAG_STORE(v), CHIP_S_MEM_BTAG_COUNT(v));
415
416 #ifdef CHIP_S_MEM_W1_BUS_START
417 #ifdef EXTENT_DEBUG
418 printf("smem: adding span 0x%lx to 0x%lx\n",
419 CHIP_S_MEM_W1_BUS_START(v), CHIP_S_MEM_W1_BUS_END(v));
420 #endif
421 error = vmem_add(svm, CHIP_S_MEM_W1_BUS_START(v),
422 CHIP_S_MEM_W1_BUS_END(v) - CHIP_S_MEM_W1_BUS_START(v) + 1,
423 VM_NOSLEEP);
424 KASSERT(error == 0);
425 #endif
426 #ifdef CHIP_S_MEM_W2_BUS_START
427 if (CHIP_S_MEM_W2_BUS_START(v) != CHIP_S_MEM_W1_BUS_START(v)) {
428 #ifdef EXTENT_DEBUG
429 printf("smem: adding span 0x%lx to 0x%lx\n",
430 CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v));
431 #endif
432 error = vmem_add(svm, CHIP_S_MEM_W2_BUS_START(v),
433 CHIP_S_MEM_W2_BUS_END(v) - CHIP_S_MEM_W2_BUS_START(v) + 1,
434 VM_NOSLEEP);
435 KASSERT(error == 0);
436 } else {
437 #ifdef EXTENT_DEBUG
438 printf("smem: window 2 (0x%lx to 0x%lx) overlaps window 1\n",
439 CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v));
440 #endif
441 }
442 #endif
443 #ifdef CHIP_S_MEM_W3_BUS_START
444 if (CHIP_S_MEM_W3_BUS_START(v) != CHIP_S_MEM_W1_BUS_START(v) &&
445 CHIP_S_MEM_W3_BUS_START(v) != CHIP_S_MEM_W2_BUS_START(v)) {
446 #ifdef EXTENT_DEBUG
447 printf("smem: adding span 0x%lx to 0x%lx\n",
448 CHIP_S_MEM_W3_BUS_START(v), CHIP_S_MEM_W3_BUS_END(v));
449 #endif
450 error = vmem_add(svm, CHIP_S_MEM_W3_BUS_START(v),
451 CHIP_S_MEM_W3_BUS_END(v) - CHIP_S_MEM_W3_BUS_START(v) + 1,
452 VM_NOSLEEP);
453 KASSERT(error == 0);
454 } else {
455 #ifdef EXTENT_DEBUG
456 printf("smem: window 3 (0x%lx to 0x%lx) overlaps window 1/2\n",
457 CHIP_S_MEM_W3_BUS_START(v), CHIP_S_MEM_W3_BUS_END(v));
458 #endif
459 }
460 #endif
461
462 #ifdef EXTENT_DEBUG
463 /* vmem_print(svm); XXX */
464 #endif
465 CHIP_S_MEM_ARENA(v) = svm;
466 }
467
468 #ifdef CHIP_D_MEM_W1_SYS_START
469 static int __C(CHIP,_xlate_addr_to_dense_handle)(void *,
470 bus_addr_t, bus_space_handle_t *);
471 static int __C(CHIP,_xlate_dense_handle_to_addr)(void *,
472 bus_space_handle_t, bus_addr_t *);
473 #endif /* CHIP_D_MEM_W1_SYS_START */
474 static int __C(CHIP,_xlate_addr_to_sparse_handle)(void *,
475 bus_addr_t, bus_space_handle_t *);
476 static int __C(CHIP,_xlate_sparse_handle_to_addr)(void *,
477 bus_space_handle_t, bus_addr_t *);
478
479 #ifdef CHIP_D_MEM_W1_SYS_START
480 static int
__C(CHIP,_xlate_addr_to_dense_handle)481 __C(CHIP,_xlate_addr_to_dense_handle)(void *v, bus_addr_t memaddr,
482 bus_space_handle_t *memhp)
483 {
484 #ifdef CHIP_D_MEM_W1_BUS_START
485 if (memaddr >= CHIP_D_MEM_W1_BUS_START(v) &&
486 memaddr <= CHIP_D_MEM_W1_BUS_END(v)) {
487 if (memhp != NULL)
488 *memhp =
489 ALPHA_PHYS_TO_K0SEG(CHIP_D_MEM_W1_SYS_START(v)) +
490 (memaddr - CHIP_D_MEM_W1_BUS_START(v));
491 return (1);
492 } else
493 #endif
494 return (0);
495 }
496
497 static int
__C(CHIP,_xlate_dense_handle_to_addr)498 __C(CHIP,_xlate_dense_handle_to_addr)(void *v, bus_space_handle_t memh,
499 bus_addr_t *memaddrp)
500 {
501
502 memh = ALPHA_K0SEG_TO_PHYS(memh);
503
504 #ifdef CHIP_D_MEM_W1_BUS_START
505 if (memh >= CHIP_D_MEM_W1_SYS_START(v) &&
506 memh <= CHIP_D_MEM_W1_SYS_END(v)) {
507 *memaddrp = CHIP_D_MEM_W1_BUS_START(v) +
508 (memh - CHIP_D_MEM_W1_SYS_START(v));
509 return (1);
510 } else
511 #endif
512 return (0);
513 }
514 #endif /* CHIP_D_MEM_W1_SYS_START */
515
516 static int
__C(CHIP,_xlate_addr_to_sparse_handle)517 __C(CHIP,_xlate_addr_to_sparse_handle)(void *v, bus_addr_t memaddr,
518 bus_space_handle_t *memhp)
519 {
520
521 #ifdef CHIP_S_MEM_W1_BUS_START
522 if (memaddr >= CHIP_S_MEM_W1_BUS_START(v) &&
523 memaddr <= CHIP_S_MEM_W1_BUS_END(v)) {
524 if (memhp != NULL)
525 *memhp =
526 (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W1_SYS_START(v)) >>
527 CHIP_ADDR_SHIFT) +
528 (memaddr - CHIP_S_MEM_W1_BUS_START(v));
529 return (1);
530 } else
531 #endif
532 #ifdef CHIP_S_MEM_W2_BUS_START
533 if (memaddr >= CHIP_S_MEM_W2_BUS_START(v) &&
534 memaddr <= CHIP_S_MEM_W2_BUS_END(v)) {
535 if (memhp != NULL)
536 *memhp =
537 (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W2_SYS_START(v)) >>
538 CHIP_ADDR_SHIFT) +
539 (memaddr - CHIP_S_MEM_W2_BUS_START(v));
540 return (1);
541 } else
542 #endif
543 #ifdef CHIP_S_MEM_W3_BUS_START
544 if (memaddr >= CHIP_S_MEM_W3_BUS_START(v) &&
545 memaddr <= CHIP_S_MEM_W3_BUS_END(v)) {
546 if (memhp != NULL)
547 *memhp =
548 (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W3_SYS_START(v)) >>
549 CHIP_ADDR_SHIFT) +
550 (memaddr - CHIP_S_MEM_W3_BUS_START(v));
551 return (1);
552 } else
553 #endif
554 return (0);
555 }
556
557 static int
__C(CHIP,_xlate_sparse_handle_to_addr)558 __C(CHIP,_xlate_sparse_handle_to_addr)(void *v, bus_space_handle_t memh,
559 bus_addr_t *memaddrp)
560 {
561
562 memh = ALPHA_K0SEG_TO_PHYS(memh << CHIP_ADDR_SHIFT) >> CHIP_ADDR_SHIFT;
563
564 #ifdef CHIP_S_MEM_W1_BUS_START
565 if ((memh << CHIP_ADDR_SHIFT) >= CHIP_S_MEM_W1_SYS_START(v) &&
566 (memh << CHIP_ADDR_SHIFT) <= CHIP_S_MEM_W1_SYS_END(v)) {
567 *memaddrp = CHIP_S_MEM_W1_BUS_START(v) +
568 (memh - (CHIP_S_MEM_W1_SYS_START(v) >> CHIP_ADDR_SHIFT));
569 return (1);
570 } else
571 #endif
572 #ifdef CHIP_S_MEM_W2_BUS_START
573 if ((memh << CHIP_ADDR_SHIFT) >= CHIP_S_MEM_W2_SYS_START(v) &&
574 (memh << CHIP_ADDR_SHIFT) <= CHIP_S_MEM_W2_SYS_END(v)) {
575 *memaddrp = CHIP_S_MEM_W2_BUS_START(v) +
576 (memh - (CHIP_S_MEM_W2_SYS_START(v) >> CHIP_ADDR_SHIFT));
577 return (1);
578 } else
579 #endif
580 #ifdef CHIP_S_MEM_W3_BUS_START
581 if ((memh << CHIP_ADDR_SHIFT) >= CHIP_S_MEM_W3_SYS_START(v) &&
582 (memh << CHIP_ADDR_SHIFT) <= CHIP_S_MEM_W3_SYS_END(v)) {
583 *memaddrp = CHIP_S_MEM_W3_BUS_START(v) +
584 (memh - (CHIP_S_MEM_W3_SYS_START(v) >> CHIP_ADDR_SHIFT));
585 return (1);
586 } else
587 #endif
588 return (0);
589 }
590
591 static int
__C(CHIP,_mem_translate)592 __C(CHIP,_mem_translate)(void *v, bus_addr_t memaddr, bus_size_t memlen,
593 int flags, struct alpha_bus_space_translation *abst)
594 {
595
596 /* XXX */
597 return (EOPNOTSUPP);
598 }
599
600 static int
__C(CHIP,_mem_get_window)601 __C(CHIP,_mem_get_window)(void *v, int window,
602 struct alpha_bus_space_translation *abst)
603 {
604
605 #ifdef CHIP_D_MEM_W1_BUS_START
606 #define FIRST_SPARSE 1
607 #else
608 #define FIRST_SPARSE 0
609 #endif
610
611 switch (window) {
612 #ifdef CHIP_D_MEM_W1_BUS_START
613 case 0:
614 abst->abst_bus_start = CHIP_D_MEM_W1_BUS_START(v);
615 abst->abst_bus_end = CHIP_D_MEM_W1_BUS_END(v);
616 abst->abst_sys_start = CHIP_D_MEM_W1_SYS_START(v);
617 abst->abst_sys_end = CHIP_D_MEM_W1_SYS_END(v);
618 abst->abst_addr_shift = 0;
619 abst->abst_size_shift = 0;
620 abst->abst_flags = ABST_DENSE;
621 break;
622 #endif
623
624 #ifdef CHIP_S_MEM_W1_BUS_START
625 case (FIRST_SPARSE):
626 abst->abst_bus_start = CHIP_S_MEM_W1_BUS_START(v);
627 abst->abst_bus_end = CHIP_S_MEM_W1_BUS_END(v);
628 abst->abst_sys_start = CHIP_S_MEM_W1_SYS_START(v);
629 abst->abst_sys_end = CHIP_S_MEM_W1_SYS_END(v);
630 abst->abst_addr_shift = CHIP_ADDR_SHIFT;
631 abst->abst_size_shift = CHIP_SIZE_SHIFT;
632 abst->abst_flags = 0;
633 break;
634 #endif
635
636 #ifdef CHIP_S_MEM_W2_BUS_START
637 case (FIRST_SPARSE + 1):
638 abst->abst_bus_start = CHIP_S_MEM_W2_BUS_START(v);
639 abst->abst_bus_end = CHIP_S_MEM_W2_BUS_END(v);
640 abst->abst_sys_start = CHIP_S_MEM_W2_SYS_START(v);
641 abst->abst_sys_end = CHIP_S_MEM_W2_SYS_END(v);
642 abst->abst_addr_shift = CHIP_ADDR_SHIFT;
643 abst->abst_size_shift = CHIP_SIZE_SHIFT;
644 abst->abst_flags = 0;
645 break;
646 #endif
647
648 #ifdef CHIP_S_MEM_W3_BUS_START
649 case (FIRST_SPARSE + 2):
650 abst->abst_bus_start = CHIP_S_MEM_W3_BUS_START(v);
651 abst->abst_bus_end = CHIP_S_MEM_W3_BUS_END(v);
652 abst->abst_sys_start = CHIP_S_MEM_W3_SYS_START(v);
653 abst->abst_sys_end = CHIP_S_MEM_W3_SYS_END(v);
654 abst->abst_addr_shift = CHIP_ADDR_SHIFT;
655 abst->abst_size_shift = CHIP_SIZE_SHIFT;
656 abst->abst_flags = 0;
657 break;
658 #endif
659 }
660
661 #undef FIRST_SPARSE
662
663 return (0);
664 }
665
666 static int
__C(CHIP,_mem_map)667 __C(CHIP,_mem_map)(void *v, bus_addr_t memaddr, bus_size_t memsize,
668 int flags, bus_space_handle_t *memhp, int acct)
669 {
670 bus_space_handle_t dh = 0, sh = 0; /* XXX -Wuninitialized */
671 int didd, dids, errord, errors, mustd, musts;
672 int prefetchable = flags & BUS_SPACE_MAP_PREFETCHABLE;
673 int linear = flags & BUS_SPACE_MAP_LINEAR;
674
675 /*
676 * XXX Too hairy to not do accounting in this space. Nothing
677 * XXX much uses this anyhow (only ISA PnP does, and only via
678 * XXX a machine-dependent hook), so we don't have to care.
679 */
680 if (acct == 0)
681 return (EOPNOTSUPP);
682
683 #ifdef CHIP_D_MEM_W1_SYS_START
684 mustd = 1;
685 if (!__C(CHIP,_xlate_addr_to_dense_handle)(v, memaddr, NULL)) {
686 /*
687 * This address isn't mapped into dense space; don't
688 * require it.
689 */
690 mustd = 0;
691 }
692 #else
693 mustd = 0;
694 #endif
695
696 /* No prefetchable space without dense. */
697 if (mustd == 0)
698 prefetchable = 0;
699
700 /*
701 * We must have dense space to map memory linearly.
702 */
703 if (linear && !prefetchable)
704 return (EOPNOTSUPP);
705
706 musts = (prefetchable == 0);
707 if (!__C(CHIP,_xlate_addr_to_sparse_handle)(v, memaddr, NULL)) {
708 /*
709 * This address isn't mapped into sparse space; don't
710 * require it.
711 */
712 musts = 0;
713 }
714
715 /*
716 * If this address isn't mapped into dense or sparse, we lose.
717 */
718 if (mustd == 0 && musts == 0) {
719 #ifdef EXTENT_DEBUG
720 printf("mem: address 0x%lx not in dense or sparse space\n",
721 memaddr);
722 #endif
723 return (EINVAL);
724 }
725
726 #ifdef EXTENT_DEBUG
727 printf("mem: allocating 0x%lx to 0x%lx\n", memaddr,
728 memaddr + memsize - 1);
729 printf("mem: %s dense, %s sparse\n", mustd ? "need" : "want",
730 musts ? "need" : "want");
731 #endif
732 #ifdef CHIP_D_MEM_W1_SYS_START
733 errord = vmem_xalloc_addr(CHIP_D_MEM_ARENA(v), memaddr, memsize,
734 VM_NOSLEEP);
735 #else
736 errord = EINVAL;
737 #endif
738 didd = (errord == 0);
739 errors = vmem_xalloc_addr(CHIP_S_MEM_ARENA(v), memaddr, memsize,
740 VM_NOSLEEP);
741 dids = (errors == 0);
742
743 #ifdef EXTENT_DEBUG
744 if (!didd)
745 printf("mem: failed to get dense (%d)\n", errord);
746 if (!dids)
747 printf("mem: failed to get sparse (%d)\n", errors);
748 #endif
749
750 if ((mustd && !didd) || (musts && !dids))
751 goto bad;
752
753 #ifdef CHIP_D_MEM_W1_SYS_START
754 if (didd && !__C(CHIP,_xlate_addr_to_dense_handle)(v, memaddr, &dh)) {
755 printf("\n");
756 #ifdef CHIP_D_MEM_W1_BUS_START
757 printf("%s: window[1]=0x%lx-0x%lx\n", __S(__C(CHIP,_mem_map)),
758 CHIP_D_MEM_W1_BUS_START(v), CHIP_D_MEM_W1_BUS_END(v));
759 #endif
760 panic("%s: don't know how to map %lx prefetchable",
761 __S(__C(CHIP,_mem_map)), memaddr);
762 }
763 #endif /* CHIP_D_MEM_W1_SYS_START */
764
765 if (dids && !__C(CHIP,_xlate_addr_to_sparse_handle)(v, memaddr, &sh)) {
766 printf("\n");
767 #ifdef CHIP_S_MEM_W1_BUS_START
768 printf("%s: window[1]=0x%lx-0x%lx\n", __S(__C(CHIP,_mem_map)),
769 CHIP_S_MEM_W1_BUS_START(v), CHIP_S_MEM_W1_BUS_END(v));
770 #endif
771 #ifdef CHIP_S_MEM_W2_BUS_START
772 printf("%s: window[2]=0x%lx-0x%lx\n", __S(__C(CHIP,_mem_map)),
773 CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v));
774 #endif
775 #ifdef CHIP_S_MEM_W3_BUS_START
776 printf("%s: window[3]=0x%lx-0x%lx\n", __S(__C(CHIP,_mem_map)),
777 CHIP_S_MEM_W3_BUS_START(v), CHIP_S_MEM_W3_BUS_END(v));
778 #endif
779 panic("%s: don't know how to map %lx non-prefetchable",
780 __S(__C(CHIP,_mem_map)), memaddr);
781 }
782
783 if (prefetchable)
784 *memhp = dh;
785 else
786 *memhp = sh;
787 return (0);
788
789 bad:
790 #ifdef EXTENT_DEBUG
791 printf("mem: failed\n");
792 #endif
793 #ifdef CHIP_D_MEM_W1_SYS_START
794 if (didd) {
795 #ifdef EXTENT_DEBUG
796 printf("mem: freeing dense\n");
797 #endif
798 vmem_xfree(CHIP_D_MEM_ARENA(v), memaddr, memsize);
799 }
800 #endif /* CHIP_D_MEM_W1_SYS_START */
801 if (dids) {
802 #ifdef EXTENT_DEBUG
803 printf("mem: freeing sparse\n");
804 #endif
805 vmem_xfree(CHIP_S_MEM_ARENA(v), memaddr, memsize);
806 }
807
808 #ifdef EXTENT_DEBUG
809 #ifdef CHIP_D_MEM_W1_SYS_START
810 /* vmem_print(CHIP_D_MEM_ARENA(v)); XXX */
811 #endif
812 /* vmem_print(CHIP_S_MEM_ARENA(v)); XXX */
813 #endif
814
815 /*
816 * return dense error if we needed it but couldn't get it, else
817 * sparse error. The error _has_ to be one of the two...
818 */
819 return (mustd && !didd ? errord : (musts && !dids ? errors : EINVAL));
820 }
821
822 static void
__C(CHIP,_mem_unmap)823 __C(CHIP,_mem_unmap)(void *v, bus_space_handle_t memh,
824 bus_size_t memsize, int acct)
825 {
826 bus_addr_t memaddr = 0;
827 #ifdef CHIP_D_MEM_W1_SYS_START
828 bus_space_handle_t temph;
829 #endif
830 int sparse, haves, haved;
831
832 if (acct == 0)
833 return;
834
835 #ifdef EXTENT_DEBUG
836 printf("mem: freeing handle 0x%lx for 0x%lx\n", memh, memsize);
837 #endif
838
839 /*
840 * Find out what space we're in.
841 */
842 sparse = ((memh >> 63) == 0);
843
844 /*
845 * Find out what address we're in in that space.
846 */
847 haves = haved = 0;
848 if (sparse)
849 haves = __C(CHIP,_xlate_sparse_handle_to_addr)(v, memh,
850 &memaddr);
851 #ifdef CHIP_D_MEM_W1_SYS_START
852 else
853 haved = __C(CHIP,_xlate_dense_handle_to_addr)(v, memh,
854 &memaddr);
855 #endif /* CHIP_D_MEM_W1_SYS_START */
856
857 if (!haves && !haved)
858 panic("%s: couldn't get addr from %s handle 0x%lx",
859 __S(__C(CHIP,_mem_unmap)), sparse ? "sparse" : "dense",
860 memh);
861
862 #ifdef CHIP_D_MEM_W1_SYS_START
863 /*
864 * Find out were/if that address lives in the other space.
865 */
866 if (sparse)
867 haved = __C(CHIP,_xlate_addr_to_dense_handle)(v, memaddr,
868 &temph);
869 else
870 haves = __C(CHIP,_xlate_addr_to_sparse_handle)(v, memaddr,
871 &temph);
872 #endif /* CHIP_D_MEM_W1_SYS_START */
873
874 /*
875 * Free any ranges we have.
876 */
877 #ifdef EXTENT_DEBUG
878 printf("mem: it's at 0x%lx (%sdense, %ssparse)\n", memaddr,
879 haved ? "" : "not ", haves ? "" : "not ");
880 #endif
881 #ifdef CHIP_D_MEM_W1_SYS_START
882 if (haved) {
883 vmem_xfree(CHIP_D_MEM_ARENA(v), memaddr, memsize);
884 }
885 #endif
886 if (haves) {
887 vmem_xfree(CHIP_S_MEM_ARENA(v), memaddr, memsize);
888 }
889 }
890
891 static int
__C(CHIP,_mem_subregion)892 __C(CHIP,_mem_subregion)(void *v, bus_space_handle_t memh,
893 bus_size_t offset, bus_size_t size, bus_space_handle_t *nmemh)
894 {
895
896 *nmemh = memh + offset;
897 return (0);
898 }
899
900 static int
__C(CHIP,_mem_alloc)901 __C(CHIP,_mem_alloc)(void *v, bus_addr_t rstart, bus_addr_t rend,
902 bus_size_t size, bus_size_t align, bus_size_t boundary, int flags,
903 bus_addr_t *addrp, bus_space_handle_t *bshp)
904 {
905
906 /* XXX XXX XXX XXX XXX XXX */
907 panic("%s not implemented", __S(__C(CHIP,_mem_alloc)));
908 }
909
910 static void
__C(CHIP,_mem_free)911 __C(CHIP,_mem_free)(void *v, bus_space_handle_t bsh, bus_size_t size)
912 {
913
914 /* XXX XXX XXX XXX XXX XXX */
915 panic("%s not implemented", __S(__C(CHIP,_mem_free)));
916 }
917
918 static void *
__C(CHIP,_mem_vaddr)919 __C(CHIP,_mem_vaddr)(void *v, bus_space_handle_t bsh)
920 {
921 #ifdef CHIP_D_MEM_W1_SYS_START
922 /*
923 * XXX should check that the range was mapped
924 * with BUS_SPACE_MAP_LINEAR for sanity
925 */
926 if ((bsh >> 63) != 0)
927 return ((void *)bsh);
928 #endif
929 return (0);
930 }
931
932 static paddr_t
__C(CHIP,_mem_mmap)933 __C(CHIP,_mem_mmap)(void *v, bus_addr_t addr, off_t off, int prot, int flags)
934 {
935 bus_space_handle_t dh = 0, sh = 0; /* XXX -Wuninitialized */
936 int linear = flags & BUS_SPACE_MAP_LINEAR;
937 int haved = 0, haves = 0;
938
939 #ifdef CHIP_D_MEM_W1_SYS_START
940 if (__C(CHIP,_xlate_addr_to_dense_handle)(v, addr + off, &dh)) {
941 haved = 1;
942 dh = ALPHA_K0SEG_TO_PHYS(dh);
943 }
944 #endif
945 if (__C(CHIP,_xlate_addr_to_sparse_handle)(v, addr + off, &sh)) {
946 haves = 1;
947 sh = ALPHA_K0SEG_TO_PHYS(sh);
948 }
949
950 if (linear) {
951 if (haved == 0)
952 return (-1);
953 return (alpha_btop(dh));
954 }
955
956 if (haves == 0)
957 return (-1);
958 return (alpha_btop(sh));
959 }
960
961 static inline void
__C(CHIP,_mem_barrier)962 __C(CHIP,_mem_barrier)(void *v, bus_space_handle_t h,
963 bus_size_t o, bus_size_t l, int f)
964 {
965
966 if ((f & BUS_SPACE_BARRIER_READ) != 0)
967 alpha_mb();
968 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0)
969 alpha_wmb();
970 }
971
972 static inline uint8_t
__C(CHIP,_mem_read_1)973 __C(CHIP,_mem_read_1)(void *v, bus_space_handle_t memh, bus_size_t off)
974 {
975 register bus_space_handle_t tmpmemh;
976 register uint32_t *port, val;
977 register uint8_t rval;
978 register int offset;
979
980 alpha_mb();
981
982 #ifdef CHIP_D_MEM_W1_SYS_START
983 if ((memh >> 63) != 0)
984 return (*(uint8_t *)(memh + off));
985 #endif
986
987 tmpmemh = memh + off;
988 offset = tmpmemh & 3;
989 port = (uint32_t *)((tmpmemh << CHIP_ADDR_SHIFT) |
990 (0 << CHIP_SIZE_SHIFT));
991 val = *port;
992 rval = ((val) >> (8 * offset)) & 0xff;
993
994 return rval;
995 }
996
997 static inline uint16_t
__C(CHIP,_mem_read_2)998 __C(CHIP,_mem_read_2)(void *v, bus_space_handle_t memh, bus_size_t off)
999 {
1000 register bus_space_handle_t tmpmemh;
1001 register uint32_t *port, val;
1002 register uint16_t rval;
1003 register int offset;
1004
1005 alpha_mb();
1006
1007 #ifdef CHIP_D_MEM_W1_SYS_START
1008 if ((memh >> 63) != 0)
1009 return (*(uint16_t *)(memh + off));
1010 #endif
1011
1012 tmpmemh = memh + off;
1013 offset = tmpmemh & 3;
1014 port = (uint32_t *)((tmpmemh << CHIP_ADDR_SHIFT) |
1015 (1 << CHIP_SIZE_SHIFT));
1016 val = *port;
1017 rval = ((val) >> (8 * offset)) & 0xffff;
1018
1019 return rval;
1020 }
1021
1022 static inline uint32_t
__C(CHIP,_mem_read_4)1023 __C(CHIP,_mem_read_4)(void *v, bus_space_handle_t memh, bus_size_t off)
1024 {
1025 register bus_space_handle_t tmpmemh;
1026 register uint32_t *port, val;
1027 register uint32_t rval;
1028
1029 alpha_mb();
1030
1031 #ifdef CHIP_D_MEM_W1_SYS_START
1032 if ((memh >> 63) != 0)
1033 return (*(uint32_t *)(memh + off));
1034 #endif
1035
1036 tmpmemh = memh + off;
1037 port = (uint32_t *)((tmpmemh << CHIP_ADDR_SHIFT) |
1038 (3 << CHIP_SIZE_SHIFT));
1039 val = *port;
1040 #if 0
1041 int offset;
1042 offset = tmpmemh & 3;
1043 rval = ((val) >> (8 * offset)) & 0xffffffff;
1044 #else
1045 rval = val;
1046 #endif
1047
1048 return rval;
1049 }
1050
1051 static inline uint64_t
__C(CHIP,_mem_read_8)1052 __C(CHIP,_mem_read_8)(void *v, bus_space_handle_t memh, bus_size_t off)
1053 {
1054
1055 alpha_mb();
1056
1057 #ifdef CHIP_D_MEM_W1_SYS_START
1058 if ((memh >> 63) != 0)
1059 return (*(uint64_t *)(memh + off));
1060 #endif
1061
1062 /* XXX XXX XXX */
1063 panic("%s not implemented", __S(__C(CHIP,_mem_read_8)));
1064 }
1065
1066 #define CHIP_mem_read_multi_N(BYTES,TYPE) \
1067 static void \
1068 __C(__C(CHIP,_mem_read_multi_),BYTES)(void *v, bus_space_handle_t h, bus_size_t o, TYPE *a, bus_size_t c) \
1069 { \
1070 \
1071 while (c-- > 0) { \
1072 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \
1073 BUS_SPACE_BARRIER_READ); \
1074 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \
1075 } \
1076 }
1077 CHIP_mem_read_multi_N(1,uint8_t)
1078 CHIP_mem_read_multi_N(2,uint16_t)
1079 CHIP_mem_read_multi_N(4,uint32_t)
1080 CHIP_mem_read_multi_N(8,uint64_t)
1081
1082 #define CHIP_mem_read_region_N(BYTES,TYPE) \
1083 static void \
1084 __C(__C(CHIP,_mem_read_region_),BYTES)(void *v, bus_space_handle_t h, bus_size_t o, TYPE *a, bus_size_t c) \
1085 { \
1086 \
1087 while (c-- > 0) { \
1088 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \
1089 o += sizeof *a; \
1090 } \
1091 }
1092 CHIP_mem_read_region_N(1,uint8_t)
1093 CHIP_mem_read_region_N(2,uint16_t)
1094 CHIP_mem_read_region_N(4,uint32_t)
1095 CHIP_mem_read_region_N(8,uint64_t)
1096
1097 static inline void
__C(CHIP,_mem_write_1)1098 __C(CHIP,_mem_write_1)(void *v, bus_space_handle_t memh, bus_size_t off, uint8_t val)
1099 {
1100 register bus_space_handle_t tmpmemh;
1101 register uint32_t *port, nval;
1102 register int offset;
1103
1104 #ifdef CHIP_D_MEM_W1_SYS_START
1105 if ((memh >> 63) != 0)
1106 (*(uint8_t *)(memh + off)) = val;
1107 else
1108 #endif
1109 {
1110 tmpmemh = memh + off;
1111 offset = tmpmemh & 3;
1112 nval = val << (8 * offset);
1113 port = (uint32_t *)((tmpmemh << CHIP_ADDR_SHIFT) |
1114 (0 << CHIP_SIZE_SHIFT));
1115 *port = nval;
1116 }
1117 alpha_mb();
1118 }
1119
1120 static inline void
__C(CHIP,_mem_write_2)1121 __C(CHIP,_mem_write_2)(void *v, bus_space_handle_t memh, bus_size_t off, uint16_t val)
1122 {
1123 register bus_space_handle_t tmpmemh;
1124 register uint32_t *port, nval;
1125 register int offset;
1126
1127 #ifdef CHIP_D_MEM_W1_SYS_START
1128 if ((memh >> 63) != 0)
1129 (*(uint16_t *)(memh + off)) = val;
1130 else
1131 #endif
1132 {
1133 tmpmemh = memh + off;
1134 offset = tmpmemh & 3;
1135 nval = val << (8 * offset);
1136 port = (uint32_t *)((tmpmemh << CHIP_ADDR_SHIFT) |
1137 (1 << CHIP_SIZE_SHIFT));
1138 *port = nval;
1139 }
1140 alpha_mb();
1141 }
1142
1143 static inline void
__C(CHIP,_mem_write_4)1144 __C(CHIP,_mem_write_4)(void *v, bus_space_handle_t memh, bus_size_t off, uint32_t val)
1145 {
1146 register bus_space_handle_t tmpmemh;
1147 register uint32_t *port, nval;
1148
1149 #ifdef CHIP_D_MEM_W1_SYS_START
1150 if ((memh >> 63) != 0)
1151 (*(uint32_t *)(memh + off)) = val;
1152 else
1153 #endif
1154 {
1155 tmpmemh = memh + off;
1156 #if 0
1157 int offset;
1158 offset = tmpmemh & 3;
1159 #endif
1160 nval = val /*<< (8 * offset)*/;
1161 port = (uint32_t *)((tmpmemh << CHIP_ADDR_SHIFT) |
1162 (3 << CHIP_SIZE_SHIFT));
1163 *port = nval;
1164 }
1165 alpha_mb();
1166 }
1167
1168 static inline void
__C(CHIP,_mem_write_8)1169 __C(CHIP,_mem_write_8)(void *v, bus_space_handle_t memh, bus_size_t off, uint64_t val)
1170 {
1171
1172 #ifdef CHIP_D_MEM_W1_SYS_START
1173 if ((memh >> 63) != 0)
1174 (*(uint64_t *)(memh + off)) = val;
1175 else
1176 #endif
1177 {
1178 /* XXX XXX XXX */
1179 panic("%s not implemented",
1180 __S(__C(CHIP,_mem_write_8)));
1181 }
1182 alpha_mb();
1183 }
1184
1185 #define CHIP_mem_write_multi_N(BYTES,TYPE) \
1186 static void \
1187 __C(__C(CHIP,_mem_write_multi_),BYTES)(void *v, bus_space_handle_t h, bus_size_t o, const TYPE *a, bus_size_t c) \
1188 { \
1189 \
1190 while (c-- > 0) { \
1191 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \
1192 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \
1193 BUS_SPACE_BARRIER_WRITE); \
1194 } \
1195 }
1196 CHIP_mem_write_multi_N(1,uint8_t)
1197 CHIP_mem_write_multi_N(2,uint16_t)
1198 CHIP_mem_write_multi_N(4,uint32_t)
1199 CHIP_mem_write_multi_N(8,uint64_t)
1200
1201 #define CHIP_mem_write_region_N(BYTES,TYPE) \
1202 static void \
1203 __C(__C(CHIP,_mem_write_region_),BYTES)(void *v, bus_space_handle_t h, bus_size_t o, const TYPE *a, bus_size_t c) \
1204 { \
1205 \
1206 while (c-- > 0) { \
1207 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \
1208 o += sizeof *a; \
1209 } \
1210 }
1211 CHIP_mem_write_region_N(1,uint8_t)
1212 CHIP_mem_write_region_N(2,uint16_t)
1213 CHIP_mem_write_region_N(4,uint32_t)
1214 CHIP_mem_write_region_N(8,uint64_t)
1215
1216 #define CHIP_mem_set_multi_N(BYTES,TYPE) \
1217 static void \
1218 __C(__C(CHIP,_mem_set_multi_),BYTES)(void *v, bus_space_handle_t h, bus_size_t o, TYPE val, bus_size_t c) \
1219 { \
1220 \
1221 while (c-- > 0) { \
1222 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \
1223 __C(CHIP,_mem_barrier)(v, h, o, sizeof val, \
1224 BUS_SPACE_BARRIER_WRITE); \
1225 } \
1226 }
1227 CHIP_mem_set_multi_N(1,uint8_t)
1228 CHIP_mem_set_multi_N(2,uint16_t)
1229 CHIP_mem_set_multi_N(4,uint32_t)
1230 CHIP_mem_set_multi_N(8,uint64_t)
1231
1232 #define CHIP_mem_set_region_N(BYTES,TYPE) \
1233 static void \
1234 __C(__C(CHIP,_mem_set_region_),BYTES)(void *v, bus_space_handle_t h, bus_size_t o, TYPE val, bus_size_t c) \
1235 { \
1236 \
1237 while (c-- > 0) { \
1238 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \
1239 o += sizeof val; \
1240 } \
1241 }
1242 CHIP_mem_set_region_N(1,uint8_t)
1243 CHIP_mem_set_region_N(2,uint16_t)
1244 CHIP_mem_set_region_N(4,uint32_t)
1245 CHIP_mem_set_region_N(8,uint64_t)
1246
1247 #define CHIP_mem_copy_region_N(BYTES) \
1248 static void \
1249 __C(__C(CHIP,_mem_copy_region_),BYTES)(void *v, bus_space_handle_t h1, bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c) \
1250 { \
1251 bus_size_t o; \
1252 \
1253 if ((h1 >> 63) != 0 && (h2 >> 63) != 0) { \
1254 memmove((void *)(h2 + o2), (void *)(h1 + o1), c * BYTES); \
1255 return; \
1256 } \
1257 \
1258 if ((h1 + o1) >= (h2 + o2)) { \
1259 /* src after dest: copy forward */ \
1260 for (o = 0; c != 0; c--, o += BYTES) \
1261 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \
1262 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \
1263 } else { \
1264 /* dest after src: copy backwards */ \
1265 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \
1266 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \
1267 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \
1268 } \
1269 }
1270 CHIP_mem_copy_region_N(1)
1271 CHIP_mem_copy_region_N(2)
1272 CHIP_mem_copy_region_N(4)
1273 CHIP_mem_copy_region_N(8)
1274