1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
5 * Copyright (c) 2013 Alexander Fedorov
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/conf.h>
35 #include <sys/kernel.h>
36 #include <sys/lock.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/mutex.h>
40 #include <sys/resource.h>
41 #include <sys/rman.h>
42 #include <sys/sysctl.h>
43 #include <sys/queue.h>
44 #include <sys/taskqueue.h>
45
46 #include <machine/bus.h>
47
48 #include <dev/ofw/ofw_bus.h>
49 #include <dev/ofw/ofw_bus_subr.h>
50
51 #include <dev/mmc/bridge.h>
52 #include <dev/mmc/mmcbrvar.h>
53 #include <dev/mmc/mmc_fdt_helpers.h>
54
55 #include <arm/allwinner/aw_mmc.h>
56 #include <dev/extres/clk/clk.h>
57 #include <dev/extres/hwreset/hwreset.h>
58 #include <dev/extres/regulator/regulator.h>
59
60 #include "opt_mmccam.h"
61
62 #ifdef MMCCAM
63 #include <cam/cam.h>
64 #include <cam/cam_ccb.h>
65 #include <cam/cam_debug.h>
66 #include <cam/cam_sim.h>
67 #include <cam/cam_xpt_sim.h>
68 #include <cam/mmc/mmc_sim.h>
69
70 #include "mmc_sim_if.h"
71 #endif
72
73 #include "mmc_pwrseq_if.h"
74
75 #define AW_MMC_MEMRES 0
76 #define AW_MMC_IRQRES 1
77 #define AW_MMC_RESSZ 2
78 #define AW_MMC_DMA_SEGS (PAGE_SIZE / sizeof(struct aw_mmc_dma_desc))
79 #define AW_MMC_DMA_DESC_SIZE (sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS)
80 #define AW_MMC_DMA_FTRGLEVEL 0x20070008
81
82 #define AW_MMC_RESET_RETRY 1000
83
84 #define CARD_ID_FREQUENCY 400000
85
86 struct aw_mmc_conf {
87 uint32_t dma_xferlen;
88 bool mask_data0;
89 bool can_calibrate;
90 bool new_timing;
91 };
92
93 static const struct aw_mmc_conf a10_mmc_conf = {
94 .dma_xferlen = 0x2000,
95 };
96
97 static const struct aw_mmc_conf a13_mmc_conf = {
98 .dma_xferlen = 0x10000,
99 };
100
101 static const struct aw_mmc_conf a64_mmc_conf = {
102 .dma_xferlen = 0x10000,
103 .mask_data0 = true,
104 .can_calibrate = true,
105 .new_timing = true,
106 };
107
108 static const struct aw_mmc_conf a64_emmc_conf = {
109 .dma_xferlen = 0x2000,
110 .can_calibrate = true,
111 };
112
113 static struct ofw_compat_data compat_data[] = {
114 {"allwinner,sun4i-a10-mmc", (uintptr_t)&a10_mmc_conf},
115 {"allwinner,sun5i-a13-mmc", (uintptr_t)&a13_mmc_conf},
116 {"allwinner,sun7i-a20-mmc", (uintptr_t)&a13_mmc_conf},
117 {"allwinner,sun50i-a64-mmc", (uintptr_t)&a64_mmc_conf},
118 {"allwinner,sun50i-a64-emmc", (uintptr_t)&a64_emmc_conf},
119 {NULL, 0}
120 };
121
122 struct aw_mmc_softc {
123 device_t aw_dev;
124 clk_t aw_clk_ahb;
125 clk_t aw_clk_mmc;
126 hwreset_t aw_rst_ahb;
127 int aw_bus_busy;
128 int aw_resid;
129 int aw_timeout;
130 struct callout aw_timeoutc;
131 struct mmc_host aw_host;
132 struct mmc_helper mmc_helper;
133 #ifdef MMCCAM
134 union ccb * ccb;
135 struct mmc_sim mmc_sim;
136 #else
137 struct mmc_request * aw_req;
138 #endif
139 struct mtx aw_mtx;
140 struct resource * aw_res[AW_MMC_RESSZ];
141 struct aw_mmc_conf * aw_mmc_conf;
142 uint32_t aw_intr;
143 uint32_t aw_intr_wait;
144 void * aw_intrhand;
145 unsigned int aw_clock;
146 device_t child;
147
148 /* Fields required for DMA access. */
149 bus_addr_t aw_dma_desc_phys;
150 bus_dmamap_t aw_dma_map;
151 bus_dma_tag_t aw_dma_tag;
152 void * aw_dma_desc;
153 bus_dmamap_t aw_dma_buf_map;
154 bus_dma_tag_t aw_dma_buf_tag;
155 int aw_dma_map_err;
156 };
157
158 static struct resource_spec aw_mmc_res_spec[] = {
159 { SYS_RES_MEMORY, 0, RF_ACTIVE },
160 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
161 { -1, 0, 0 }
162 };
163
164 static int aw_mmc_probe(device_t);
165 static int aw_mmc_attach(device_t);
166 static int aw_mmc_detach(device_t);
167 static int aw_mmc_setup_dma(struct aw_mmc_softc *);
168 static void aw_mmc_teardown_dma(struct aw_mmc_softc *sc);
169 static int aw_mmc_reset(struct aw_mmc_softc *);
170 static int aw_mmc_init(struct aw_mmc_softc *);
171 static void aw_mmc_intr(void *);
172 static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t);
173 static void aw_mmc_helper_cd_handler(device_t, bool);
174
175 static void aw_mmc_print_error(uint32_t);
176 static int aw_mmc_update_ios(device_t, device_t);
177 static int aw_mmc_request(device_t, device_t, struct mmc_request *);
178
179 #ifndef MMCCAM
180 static int aw_mmc_get_ro(device_t, device_t);
181 static int aw_mmc_acquire_host(device_t, device_t);
182 static int aw_mmc_release_host(device_t, device_t);
183 #endif
184
185 #define AW_MMC_LOCK(_sc) mtx_lock(&(_sc)->aw_mtx)
186 #define AW_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->aw_mtx)
187 #define AW_MMC_READ_4(_sc, _reg) \
188 bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg)
189 #define AW_MMC_WRITE_4(_sc, _reg, _value) \
190 bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value)
191
192 SYSCTL_NODE(_hw, OID_AUTO, aw_mmc, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
193 "aw_mmc driver");
194
195 static int aw_mmc_debug = 0;
196 SYSCTL_INT(_hw_aw_mmc, OID_AUTO, debug, CTLFLAG_RWTUN, &aw_mmc_debug, 0,
197 "Debug level bit0=card changes bit1=ios changes, bit2=interrupts, bit3=commands");
198 #define AW_MMC_DEBUG_CARD 0x1
199 #define AW_MMC_DEBUG_IOS 0x2
200 #define AW_MMC_DEBUG_INT 0x4
201 #define AW_MMC_DEBUG_CMD 0x8
202
203 #ifdef MMCCAM
204 static int
aw_mmc_get_tran_settings(device_t dev,struct ccb_trans_settings_mmc * cts)205 aw_mmc_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts)
206 {
207 struct aw_mmc_softc *sc;
208
209 sc = device_get_softc(dev);
210
211 cts->host_ocr = sc->aw_host.host_ocr;
212 cts->host_f_min = sc->aw_host.f_min;
213 cts->host_f_max = sc->aw_host.f_max;
214 cts->host_caps = sc->aw_host.caps;
215 cts->host_max_data = (sc->aw_mmc_conf->dma_xferlen *
216 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE;
217 memcpy(&cts->ios, &sc->aw_host.ios, sizeof(struct mmc_ios));
218
219 return (0);
220 }
221
222 static int
aw_mmc_set_tran_settings(device_t dev,struct ccb_trans_settings_mmc * cts)223 aw_mmc_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts)
224 {
225 struct aw_mmc_softc *sc;
226 struct mmc_ios *ios;
227 struct mmc_ios *new_ios;
228
229 sc = device_get_softc(dev);
230 ios = &sc->aw_host.ios;
231 new_ios = &cts->ios;
232
233 /* Update only requested fields */
234 if (cts->ios_valid & MMC_CLK) {
235 ios->clock = new_ios->clock;
236 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
237 device_printf(sc->aw_dev, "Clock => %d\n", ios->clock);
238 }
239 if (cts->ios_valid & MMC_VDD) {
240 ios->vdd = new_ios->vdd;
241 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
242 device_printf(sc->aw_dev, "VDD => %d\n", ios->vdd);
243 }
244 if (cts->ios_valid & MMC_CS) {
245 ios->chip_select = new_ios->chip_select;
246 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
247 device_printf(sc->aw_dev, "CS => %d\n", ios->chip_select);
248 }
249 if (cts->ios_valid & MMC_BW) {
250 ios->bus_width = new_ios->bus_width;
251 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
252 device_printf(sc->aw_dev, "Bus width => %d\n", ios->bus_width);
253 }
254 if (cts->ios_valid & MMC_PM) {
255 ios->power_mode = new_ios->power_mode;
256 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
257 device_printf(sc->aw_dev, "Power mode => %d\n", ios->power_mode);
258 }
259 if (cts->ios_valid & MMC_BT) {
260 ios->timing = new_ios->timing;
261 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
262 device_printf(sc->aw_dev, "Timing => %d\n", ios->timing);
263 }
264 if (cts->ios_valid & MMC_BM) {
265 ios->bus_mode = new_ios->bus_mode;
266 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
267 device_printf(sc->aw_dev, "Bus mode => %d\n", ios->bus_mode);
268 }
269
270 return (aw_mmc_update_ios(sc->aw_dev, NULL));
271 }
272
273 static int
aw_mmc_cam_request(device_t dev,union ccb * ccb)274 aw_mmc_cam_request(device_t dev, union ccb *ccb)
275 {
276 struct aw_mmc_softc *sc;
277 struct ccb_mmcio *mmcio;
278
279 sc = device_get_softc(dev);
280 mmcio = &ccb->mmcio;
281
282 AW_MMC_LOCK(sc);
283
284 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) {
285 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
286 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags,
287 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0,
288 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0);
289 }
290 if (mmcio->cmd.data != NULL) {
291 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0)
292 panic("data->len = %d, data->flags = %d -- something is b0rked",
293 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags);
294 }
295 if (sc->ccb != NULL) {
296 device_printf(sc->aw_dev, "Controller still has an active command\n");
297 return (EBUSY);
298 }
299 sc->ccb = ccb;
300 /* aw_mmc_request locks again */
301 AW_MMC_UNLOCK(sc);
302 aw_mmc_request(sc->aw_dev, NULL, NULL);
303
304 return (0);
305 }
306
307 static void
aw_mmc_cam_poll(device_t dev)308 aw_mmc_cam_poll(device_t dev)
309 {
310 struct aw_mmc_softc *sc;
311
312 sc = device_get_softc(dev);
313 aw_mmc_intr(sc);
314 }
315 #endif /* MMCCAM */
316
317 static void
aw_mmc_helper_cd_handler(device_t dev,bool present)318 aw_mmc_helper_cd_handler(device_t dev, bool present)
319 {
320 struct aw_mmc_softc *sc;
321
322 sc = device_get_softc(dev);
323 #ifdef MMCCAM
324 mmc_cam_sim_discover(&sc->mmc_sim);
325 #else
326 bus_topo_lock();
327 if (present) {
328 if (sc->child == NULL) {
329 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD))
330 device_printf(sc->aw_dev, "Card inserted\n");
331
332 sc->child = device_add_child(sc->aw_dev, "mmc", -1);
333 if (sc->child) {
334 device_set_ivars(sc->child, sc);
335 (void)device_probe_and_attach(sc->child);
336 }
337 }
338 } else {
339 /* Card isn't present, detach if necessary */
340 if (sc->child != NULL) {
341 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD))
342 device_printf(sc->aw_dev, "Card removed\n");
343
344 device_delete_child(sc->aw_dev, sc->child);
345 sc->child = NULL;
346 }
347 }
348 bus_topo_unlock();
349 #endif /* MMCCAM */
350 }
351
352 static int
aw_mmc_probe(device_t dev)353 aw_mmc_probe(device_t dev)
354 {
355
356 if (!ofw_bus_status_okay(dev))
357 return (ENXIO);
358 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
359 return (ENXIO);
360
361 device_set_desc(dev, "Allwinner Integrated MMC/SD controller");
362
363 return (BUS_PROBE_DEFAULT);
364 }
365
366 static int
aw_mmc_attach(device_t dev)367 aw_mmc_attach(device_t dev)
368 {
369 struct aw_mmc_softc *sc;
370 struct sysctl_ctx_list *ctx;
371 struct sysctl_oid_list *tree;
372 int error;
373
374 sc = device_get_softc(dev);
375 sc->aw_dev = dev;
376
377 sc->aw_mmc_conf = (struct aw_mmc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
378
379 #ifndef MMCCAM
380 sc->aw_req = NULL;
381 #endif
382 if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) {
383 device_printf(dev, "cannot allocate device resources\n");
384 return (ENXIO);
385 }
386 if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES],
387 INTR_TYPE_NET | INTR_MPSAFE, NULL, aw_mmc_intr, sc,
388 &sc->aw_intrhand)) {
389 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res);
390 device_printf(dev, "cannot setup interrupt handler\n");
391 return (ENXIO);
392 }
393 mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc",
394 MTX_DEF);
395 callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0);
396
397 /* De-assert reset */
398 if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) {
399 error = hwreset_deassert(sc->aw_rst_ahb);
400 if (error != 0) {
401 device_printf(dev, "cannot de-assert reset\n");
402 goto fail;
403 }
404 }
405
406 /* Activate the module clock. */
407 error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb);
408 if (error != 0) {
409 device_printf(dev, "cannot get ahb clock\n");
410 goto fail;
411 }
412 error = clk_enable(sc->aw_clk_ahb);
413 if (error != 0) {
414 device_printf(dev, "cannot enable ahb clock\n");
415 goto fail;
416 }
417 error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc);
418 if (error != 0) {
419 device_printf(dev, "cannot get mmc clock\n");
420 goto fail;
421 }
422 error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY,
423 CLK_SET_ROUND_DOWN);
424 if (error != 0) {
425 device_printf(dev, "cannot init mmc clock\n");
426 goto fail;
427 }
428 error = clk_enable(sc->aw_clk_mmc);
429 if (error != 0) {
430 device_printf(dev, "cannot enable mmc clock\n");
431 goto fail;
432 }
433
434 sc->aw_timeout = 10;
435 ctx = device_get_sysctl_ctx(dev);
436 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
437 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW,
438 &sc->aw_timeout, 0, "Request timeout in seconds");
439
440 /* Soft Reset controller. */
441 if (aw_mmc_reset(sc) != 0) {
442 device_printf(dev, "cannot reset the controller\n");
443 goto fail;
444 }
445
446 if (aw_mmc_setup_dma(sc) != 0) {
447 device_printf(sc->aw_dev, "Couldn't setup DMA!\n");
448 goto fail;
449 }
450
451 /* Set some defaults for freq and supported mode */
452 sc->aw_host.f_min = 400000;
453 sc->aw_host.f_max = 52000000;
454 sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
455 sc->aw_host.caps |= MMC_CAP_HSPEED | MMC_CAP_SIGNALING_330;
456 mmc_fdt_parse(dev, 0, &sc->mmc_helper, &sc->aw_host);
457 mmc_fdt_gpio_setup(dev, 0, &sc->mmc_helper, aw_mmc_helper_cd_handler);
458
459 #ifdef MMCCAM
460 sc->ccb = NULL;
461
462 if (mmc_cam_sim_alloc(dev, "aw_mmc", &sc->mmc_sim) != 0) {
463 device_printf(dev, "cannot alloc cam sim\n");
464 goto fail;
465 }
466 #endif /* MMCCAM */
467
468 return (0);
469
470 fail:
471 callout_drain(&sc->aw_timeoutc);
472 mtx_destroy(&sc->aw_mtx);
473 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand);
474 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res);
475
476 return (ENXIO);
477 }
478
479 static int
aw_mmc_detach(device_t dev)480 aw_mmc_detach(device_t dev)
481 {
482 struct aw_mmc_softc *sc;
483 device_t d;
484
485 sc = device_get_softc(dev);
486
487 clk_disable(sc->aw_clk_mmc);
488 clk_disable(sc->aw_clk_ahb);
489 hwreset_assert(sc->aw_rst_ahb);
490
491 mmc_fdt_gpio_teardown(&sc->mmc_helper);
492
493 callout_drain(&sc->aw_timeoutc);
494
495 AW_MMC_LOCK(sc);
496 d = sc->child;
497 sc->child = NULL;
498 AW_MMC_UNLOCK(sc);
499 if (d != NULL)
500 device_delete_child(sc->aw_dev, d);
501
502 aw_mmc_teardown_dma(sc);
503
504 mtx_destroy(&sc->aw_mtx);
505
506 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand);
507 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res);
508
509 #ifdef MMCCAM
510 mmc_cam_sim_free(&sc->mmc_sim);
511 #endif
512
513 return (0);
514 }
515
516 static void
aw_dma_desc_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int err)517 aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
518 {
519 struct aw_mmc_softc *sc;
520
521 sc = (struct aw_mmc_softc *)arg;
522 if (err) {
523 sc->aw_dma_map_err = err;
524 return;
525 }
526 sc->aw_dma_desc_phys = segs[0].ds_addr;
527 }
528
529 static int
aw_mmc_setup_dma(struct aw_mmc_softc * sc)530 aw_mmc_setup_dma(struct aw_mmc_softc *sc)
531 {
532 int error;
533
534 /* Allocate the DMA descriptor memory. */
535 error = bus_dma_tag_create(
536 bus_get_dma_tag(sc->aw_dev), /* parent */
537 AW_MMC_DMA_ALIGN, 0, /* align, boundary */
538 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
539 BUS_SPACE_MAXADDR, /* highaddr */
540 NULL, NULL, /* filter, filterarg*/
541 AW_MMC_DMA_DESC_SIZE, 1, /* maxsize, nsegment */
542 AW_MMC_DMA_DESC_SIZE, /* maxsegsize */
543 0, /* flags */
544 NULL, NULL, /* lock, lockarg*/
545 &sc->aw_dma_tag);
546 if (error)
547 return (error);
548
549 error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc,
550 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
551 &sc->aw_dma_map);
552 if (error)
553 return (error);
554
555 error = bus_dmamap_load(sc->aw_dma_tag,
556 sc->aw_dma_map,
557 sc->aw_dma_desc, AW_MMC_DMA_DESC_SIZE,
558 aw_dma_desc_cb, sc, 0);
559 if (error)
560 return (error);
561 if (sc->aw_dma_map_err)
562 return (sc->aw_dma_map_err);
563
564 /* Create the DMA map for data transfers. */
565 error = bus_dma_tag_create(
566 bus_get_dma_tag(sc->aw_dev), /* parent */
567 AW_MMC_DMA_ALIGN, 0, /* align, boundary */
568 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
569 BUS_SPACE_MAXADDR, /* highaddr */
570 NULL, NULL, /* filter, filterarg*/
571 sc->aw_mmc_conf->dma_xferlen *
572 AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS, /* maxsize, nsegments */
573 sc->aw_mmc_conf->dma_xferlen, /* maxsegsize */
574 BUS_DMA_ALLOCNOW, /* flags */
575 NULL, NULL, /* lock, lockarg*/
576 &sc->aw_dma_buf_tag);
577 if (error)
578 return (error);
579 error = bus_dmamap_create(sc->aw_dma_buf_tag, 0,
580 &sc->aw_dma_buf_map);
581 if (error)
582 return (error);
583
584 return (0);
585 }
586
587 static void
aw_mmc_teardown_dma(struct aw_mmc_softc * sc)588 aw_mmc_teardown_dma(struct aw_mmc_softc *sc)
589 {
590
591 bus_dmamap_unload(sc->aw_dma_tag, sc->aw_dma_map);
592 bus_dmamem_free(sc->aw_dma_tag, sc->aw_dma_desc, sc->aw_dma_map);
593 if (bus_dma_tag_destroy(sc->aw_dma_tag) != 0)
594 device_printf(sc->aw_dev, "Cannot destroy the dma tag\n");
595
596 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map);
597 bus_dmamap_destroy(sc->aw_dma_buf_tag, sc->aw_dma_buf_map);
598 if (bus_dma_tag_destroy(sc->aw_dma_buf_tag) != 0)
599 device_printf(sc->aw_dev, "Cannot destroy the dma buf tag\n");
600 }
601
602 static void
aw_dma_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int err)603 aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
604 {
605 int i;
606 struct aw_mmc_dma_desc *dma_desc;
607 struct aw_mmc_softc *sc;
608
609 sc = (struct aw_mmc_softc *)arg;
610 sc->aw_dma_map_err = err;
611
612 if (err)
613 return;
614
615 dma_desc = sc->aw_dma_desc;
616 for (i = 0; i < nsegs; i++) {
617 if (segs[i].ds_len == sc->aw_mmc_conf->dma_xferlen)
618 dma_desc[i].buf_size = 0; /* Size of 0 indicate max len */
619 else
620 dma_desc[i].buf_size = segs[i].ds_len;
621 dma_desc[i].buf_addr = segs[i].ds_addr;
622 dma_desc[i].config = AW_MMC_DMA_CONFIG_CH |
623 AW_MMC_DMA_CONFIG_OWN | AW_MMC_DMA_CONFIG_DIC;
624
625 dma_desc[i].next = sc->aw_dma_desc_phys +
626 ((i + 1) * sizeof(struct aw_mmc_dma_desc));
627 }
628
629 dma_desc[0].config |= AW_MMC_DMA_CONFIG_FD;
630 dma_desc[nsegs - 1].config |= AW_MMC_DMA_CONFIG_LD |
631 AW_MMC_DMA_CONFIG_ER;
632 dma_desc[nsegs - 1].config &= ~AW_MMC_DMA_CONFIG_DIC;
633 dma_desc[nsegs - 1].next = 0;
634 }
635
636 static int
aw_mmc_prepare_dma(struct aw_mmc_softc * sc)637 aw_mmc_prepare_dma(struct aw_mmc_softc *sc)
638 {
639 bus_dmasync_op_t sync_op;
640 int error;
641 struct mmc_command *cmd;
642 uint32_t val;
643
644 #ifdef MMCCAM
645 cmd = &sc->ccb->mmcio.cmd;
646 #else
647 cmd = sc->aw_req->cmd;
648 #endif
649 if (cmd->data->len > (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS))
650 return (EFBIG);
651 error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map,
652 cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0);
653 if (error)
654 return (error);
655 if (sc->aw_dma_map_err)
656 return (sc->aw_dma_map_err);
657
658 if (cmd->data->flags & MMC_DATA_WRITE)
659 sync_op = BUS_DMASYNC_PREWRITE;
660 else
661 sync_op = BUS_DMASYNC_PREREAD;
662 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op);
663 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE);
664
665 /* Enable DMA */
666 val = AW_MMC_READ_4(sc, AW_MMC_GCTL);
667 val &= ~AW_MMC_GCTL_FIFO_AC_MOD;
668 val |= AW_MMC_GCTL_DMA_ENB;
669 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val);
670
671 /* Reset DMA */
672 val |= AW_MMC_GCTL_DMA_RST;
673 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val);
674
675 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST);
676 AW_MMC_WRITE_4(sc, AW_MMC_DMAC,
677 AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST);
678
679 /* Enable RX or TX DMA interrupt */
680 val = AW_MMC_READ_4(sc, AW_MMC_IDIE);
681 if (cmd->data->flags & MMC_DATA_WRITE)
682 val |= AW_MMC_IDST_TX_INT;
683 else
684 val |= AW_MMC_IDST_RX_INT;
685 AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val);
686
687 /* Set DMA descritptor list address */
688 AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys);
689
690 /* FIFO trigger level */
691 AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL);
692
693 return (0);
694 }
695
696 static int
aw_mmc_reset(struct aw_mmc_softc * sc)697 aw_mmc_reset(struct aw_mmc_softc *sc)
698 {
699 uint32_t reg;
700 int timeout;
701
702 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
703 reg |= AW_MMC_GCTL_RESET;
704 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
705 timeout = AW_MMC_RESET_RETRY;
706 while (--timeout > 0) {
707 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_GCTL_RESET) == 0)
708 break;
709 DELAY(100);
710 }
711 if (timeout == 0)
712 return (ETIMEDOUT);
713
714 return (0);
715 }
716
717 static int
aw_mmc_init(struct aw_mmc_softc * sc)718 aw_mmc_init(struct aw_mmc_softc *sc)
719 {
720 uint32_t reg;
721 int ret;
722
723 ret = aw_mmc_reset(sc);
724 if (ret != 0)
725 return (ret);
726
727 /* Set the timeout. */
728 AW_MMC_WRITE_4(sc, AW_MMC_TMOR,
729 AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) |
730 AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK));
731
732 /* Unmask interrupts. */
733 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0);
734
735 /* Clear pending interrupts. */
736 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
737
738 /* Debug register, undocumented */
739 AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb);
740
741 /* Function select register */
742 AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000);
743
744 AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff);
745
746 /* Enable interrupts and disable AHB access. */
747 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
748 reg |= AW_MMC_GCTL_INT_ENB;
749 reg &= ~AW_MMC_GCTL_FIFO_AC_MOD;
750 reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS;
751 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
752
753 return (0);
754 }
755
756 static void
aw_mmc_req_done(struct aw_mmc_softc * sc)757 aw_mmc_req_done(struct aw_mmc_softc *sc)
758 {
759 struct mmc_command *cmd;
760 #ifdef MMCCAM
761 union ccb *ccb;
762 #else
763 struct mmc_request *req;
764 #endif
765 uint32_t val, mask;
766 int retry;
767
768 #ifdef MMCCAM
769 ccb = sc->ccb;
770 cmd = &ccb->mmcio.cmd;
771 #else
772 cmd = sc->aw_req->cmd;
773 #endif
774 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) {
775 device_printf(sc->aw_dev, "%s: cmd %d err %d\n", __func__, cmd->opcode, cmd->error);
776 }
777 if (cmd->error != MMC_ERR_NONE) {
778 /* Reset the FIFO and DMA engines. */
779 mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST;
780 val = AW_MMC_READ_4(sc, AW_MMC_GCTL);
781 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask);
782
783 retry = AW_MMC_RESET_RETRY;
784 while (--retry > 0) {
785 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) &
786 AW_MMC_GCTL_RESET) == 0)
787 break;
788 DELAY(100);
789 }
790 if (retry == 0)
791 device_printf(sc->aw_dev,
792 "timeout resetting DMA/FIFO\n");
793 aw_mmc_update_clock(sc, 1);
794 }
795
796 if (!dumping)
797 callout_stop(&sc->aw_timeoutc);
798 sc->aw_intr = 0;
799 sc->aw_resid = 0;
800 sc->aw_dma_map_err = 0;
801 sc->aw_intr_wait = 0;
802 #ifdef MMCCAM
803 sc->ccb = NULL;
804 ccb->ccb_h.status =
805 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR);
806 xpt_done(ccb);
807 #else
808 req = sc->aw_req;
809 sc->aw_req = NULL;
810 req->done(req);
811 #endif
812 }
813
814 static void
aw_mmc_req_ok(struct aw_mmc_softc * sc)815 aw_mmc_req_ok(struct aw_mmc_softc *sc)
816 {
817 int timeout;
818 struct mmc_command *cmd;
819 uint32_t status;
820
821 timeout = 1000;
822 while (--timeout > 0) {
823 status = AW_MMC_READ_4(sc, AW_MMC_STAR);
824 if ((status & AW_MMC_STAR_CARD_BUSY) == 0)
825 break;
826 DELAY(1000);
827 }
828 #ifdef MMCCAM
829 cmd = &sc->ccb->mmcio.cmd;
830 #else
831 cmd = sc->aw_req->cmd;
832 #endif
833 if (timeout == 0) {
834 cmd->error = MMC_ERR_FAILED;
835 aw_mmc_req_done(sc);
836 return;
837 }
838 if (cmd->flags & MMC_RSP_PRESENT) {
839 if (cmd->flags & MMC_RSP_136) {
840 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3);
841 cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2);
842 cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1);
843 cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0);
844 } else
845 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0);
846 }
847 /* All data has been transferred ? */
848 if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len)
849 cmd->error = MMC_ERR_FAILED;
850 aw_mmc_req_done(sc);
851 }
852
853 static inline void
set_mmc_error(struct aw_mmc_softc * sc,int error_code)854 set_mmc_error(struct aw_mmc_softc *sc, int error_code)
855 {
856 #ifdef MMCCAM
857 sc->ccb->mmcio.cmd.error = error_code;
858 #else
859 sc->aw_req->cmd->error = error_code;
860 #endif
861 }
862
863 static void
aw_mmc_timeout(void * arg)864 aw_mmc_timeout(void *arg)
865 {
866 struct aw_mmc_softc *sc;
867
868 sc = (struct aw_mmc_softc *)arg;
869 #ifdef MMCCAM
870 if (sc->ccb != NULL) {
871 #else
872 if (sc->aw_req != NULL) {
873 #endif
874 device_printf(sc->aw_dev, "controller timeout\n");
875 set_mmc_error(sc, MMC_ERR_TIMEOUT);
876 aw_mmc_req_done(sc);
877 } else
878 device_printf(sc->aw_dev,
879 "Spurious timeout - no active request\n");
880 }
881
882 static void
883 aw_mmc_print_error(uint32_t err)
884 {
885 if(err & AW_MMC_INT_RESP_ERR)
886 printf("AW_MMC_INT_RESP_ERR ");
887 if (err & AW_MMC_INT_RESP_CRC_ERR)
888 printf("AW_MMC_INT_RESP_CRC_ERR ");
889 if (err & AW_MMC_INT_DATA_CRC_ERR)
890 printf("AW_MMC_INT_DATA_CRC_ERR ");
891 if (err & AW_MMC_INT_RESP_TIMEOUT)
892 printf("AW_MMC_INT_RESP_TIMEOUT ");
893 if (err & AW_MMC_INT_FIFO_RUN_ERR)
894 printf("AW_MMC_INT_FIFO_RUN_ERR ");
895 if (err & AW_MMC_INT_CMD_BUSY)
896 printf("AW_MMC_INT_CMD_BUSY ");
897 if (err & AW_MMC_INT_DATA_START_ERR)
898 printf("AW_MMC_INT_DATA_START_ERR ");
899 if (err & AW_MMC_INT_DATA_END_BIT_ERR)
900 printf("AW_MMC_INT_DATA_END_BIT_ERR");
901 printf("\n");
902 }
903
904 static void
905 aw_mmc_intr(void *arg)
906 {
907 bus_dmasync_op_t sync_op;
908 struct aw_mmc_softc *sc;
909 struct mmc_data *data;
910 uint32_t idst, imask, rint;
911
912 sc = (struct aw_mmc_softc *)arg;
913 AW_MMC_LOCK(sc);
914 rint = AW_MMC_READ_4(sc, AW_MMC_RISR);
915 idst = AW_MMC_READ_4(sc, AW_MMC_IDST);
916 imask = AW_MMC_READ_4(sc, AW_MMC_IMKR);
917 if (idst == 0 && imask == 0 && rint == 0) {
918 AW_MMC_UNLOCK(sc);
919 return;
920 }
921 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT)) {
922 device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n",
923 idst, imask, rint);
924 }
925 #ifdef MMCCAM
926 if (sc->ccb == NULL) {
927 #else
928 if (sc->aw_req == NULL) {
929 #endif
930 device_printf(sc->aw_dev,
931 "Spurious interrupt - no active request, rint: 0x%08X\n",
932 rint);
933 aw_mmc_print_error(rint);
934 goto end;
935 }
936 if (rint & AW_MMC_INT_ERR_BIT) {
937 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT)) {
938 device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint);
939 aw_mmc_print_error(rint);
940 }
941 if (rint & AW_MMC_INT_RESP_TIMEOUT)
942 set_mmc_error(sc, MMC_ERR_TIMEOUT);
943 else
944 set_mmc_error(sc, MMC_ERR_FAILED);
945 aw_mmc_req_done(sc);
946 goto end;
947 }
948 if (idst & AW_MMC_IDST_ERROR) {
949 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT))
950 device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst);
951 set_mmc_error(sc, MMC_ERR_FAILED);
952 aw_mmc_req_done(sc);
953 goto end;
954 }
955
956 sc->aw_intr |= rint;
957 #ifdef MMCCAM
958 data = sc->ccb->mmcio.cmd.data;
959 #else
960 data = sc->aw_req->cmd->data;
961 #endif
962 if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) {
963 if (data->flags & MMC_DATA_WRITE)
964 sync_op = BUS_DMASYNC_POSTWRITE;
965 else
966 sync_op = BUS_DMASYNC_POSTREAD;
967 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map,
968 sync_op);
969 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map,
970 BUS_DMASYNC_POSTWRITE);
971 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map);
972 sc->aw_resid = data->len >> 2;
973 }
974 if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait)
975 aw_mmc_req_ok(sc);
976
977 end:
978 AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst);
979 AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint);
980 AW_MMC_UNLOCK(sc);
981 }
982
983 static int
984 aw_mmc_request(device_t bus, device_t child, struct mmc_request *req)
985 {
986 int blksz;
987 struct aw_mmc_softc *sc;
988 struct mmc_command *cmd;
989 uint32_t cmdreg, imask;
990 int err;
991
992 sc = device_get_softc(bus);
993
994 AW_MMC_LOCK(sc);
995 #ifdef MMCCAM
996 KASSERT(req == NULL, ("req should be NULL in MMCCAM case!"));
997 /*
998 * For MMCCAM, sc->ccb has been NULL-checked and populated
999 * by aw_mmc_cam_request() already.
1000 */
1001 cmd = &sc->ccb->mmcio.cmd;
1002 #else
1003 if (sc->aw_req) {
1004 AW_MMC_UNLOCK(sc);
1005 return (EBUSY);
1006 }
1007 sc->aw_req = req;
1008 cmd = req->cmd;
1009
1010 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) {
1011 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1012 cmd->opcode, cmd->arg, cmd->flags,
1013 cmd->data != NULL ? (unsigned int)cmd->data->len : 0,
1014 cmd->data != NULL ? cmd->data->flags: 0);
1015 }
1016 #endif
1017 cmdreg = AW_MMC_CMDR_LOAD;
1018 imask = AW_MMC_INT_ERR_BIT;
1019 sc->aw_intr_wait = 0;
1020 sc->aw_intr = 0;
1021 sc->aw_resid = 0;
1022 cmd->error = MMC_ERR_NONE;
1023
1024 if (cmd->opcode == MMC_GO_IDLE_STATE)
1025 cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ;
1026
1027 if (cmd->flags & MMC_RSP_PRESENT)
1028 cmdreg |= AW_MMC_CMDR_RESP_RCV;
1029 if (cmd->flags & MMC_RSP_136)
1030 cmdreg |= AW_MMC_CMDR_LONG_RESP;
1031 if (cmd->flags & MMC_RSP_CRC)
1032 cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC;
1033
1034 if (cmd->data) {
1035 cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER;
1036
1037 if (cmd->data->flags & MMC_DATA_MULTI) {
1038 cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG;
1039 imask |= AW_MMC_INT_AUTO_STOP_DONE;
1040 sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE;
1041 } else {
1042 sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER;
1043 imask |= AW_MMC_INT_DATA_OVER;
1044 }
1045 if (cmd->data->flags & MMC_DATA_WRITE)
1046 cmdreg |= AW_MMC_CMDR_DIR_WRITE;
1047 #ifdef MMCCAM
1048 if (cmd->data->flags & MMC_DATA_BLOCK_SIZE) {
1049 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, cmd->data->block_size);
1050 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len);
1051 } else
1052 #endif
1053 {
1054 blksz = min(cmd->data->len, MMC_SECTOR_SIZE);
1055 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz);
1056 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len);
1057 }
1058 } else {
1059 imask |= AW_MMC_INT_CMD_DONE;
1060 }
1061
1062 /* Enable the interrupts we are interested in */
1063 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, imask);
1064 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
1065
1066 /* Enable auto stop if needed */
1067 AW_MMC_WRITE_4(sc, AW_MMC_A12A,
1068 cmdreg & AW_MMC_CMDR_STOP_CMD_FLAG ? 0 : 0xffff);
1069
1070 /* Write the command argument */
1071 AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg);
1072
1073 /*
1074 * If we don't have data start the request
1075 * if we do prepare the dma request and start the request
1076 */
1077 if (cmd->data == NULL) {
1078 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode);
1079 } else {
1080 err = aw_mmc_prepare_dma(sc);
1081 if (err != 0)
1082 device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err);
1083
1084 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode);
1085 }
1086
1087 if (!dumping) {
1088 callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz,
1089 aw_mmc_timeout, sc);
1090 }
1091 AW_MMC_UNLOCK(sc);
1092
1093 return (0);
1094 }
1095
1096 static int
1097 aw_mmc_read_ivar(device_t bus, device_t child, int which,
1098 uintptr_t *result)
1099 {
1100 struct aw_mmc_softc *sc;
1101
1102 sc = device_get_softc(bus);
1103 switch (which) {
1104 default:
1105 return (EINVAL);
1106 case MMCBR_IVAR_BUS_MODE:
1107 *(int *)result = sc->aw_host.ios.bus_mode;
1108 break;
1109 case MMCBR_IVAR_BUS_WIDTH:
1110 *(int *)result = sc->aw_host.ios.bus_width;
1111 break;
1112 case MMCBR_IVAR_CHIP_SELECT:
1113 *(int *)result = sc->aw_host.ios.chip_select;
1114 break;
1115 case MMCBR_IVAR_CLOCK:
1116 *(int *)result = sc->aw_host.ios.clock;
1117 break;
1118 case MMCBR_IVAR_F_MIN:
1119 *(int *)result = sc->aw_host.f_min;
1120 break;
1121 case MMCBR_IVAR_F_MAX:
1122 *(int *)result = sc->aw_host.f_max;
1123 break;
1124 case MMCBR_IVAR_HOST_OCR:
1125 *(int *)result = sc->aw_host.host_ocr;
1126 break;
1127 case MMCBR_IVAR_MODE:
1128 *(int *)result = sc->aw_host.mode;
1129 break;
1130 case MMCBR_IVAR_OCR:
1131 *(int *)result = sc->aw_host.ocr;
1132 break;
1133 case MMCBR_IVAR_POWER_MODE:
1134 *(int *)result = sc->aw_host.ios.power_mode;
1135 break;
1136 case MMCBR_IVAR_VDD:
1137 *(int *)result = sc->aw_host.ios.vdd;
1138 break;
1139 case MMCBR_IVAR_VCCQ:
1140 *(int *)result = sc->aw_host.ios.vccq;
1141 break;
1142 case MMCBR_IVAR_CAPS:
1143 *(int *)result = sc->aw_host.caps;
1144 break;
1145 case MMCBR_IVAR_TIMING:
1146 *(int *)result = sc->aw_host.ios.timing;
1147 break;
1148 case MMCBR_IVAR_MAX_DATA:
1149 *(int *)result = (sc->aw_mmc_conf->dma_xferlen *
1150 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE;
1151 break;
1152 case MMCBR_IVAR_RETUNE_REQ:
1153 *(int *)result = retune_req_none;
1154 break;
1155 }
1156
1157 return (0);
1158 }
1159
1160 static int
1161 aw_mmc_write_ivar(device_t bus, device_t child, int which,
1162 uintptr_t value)
1163 {
1164 struct aw_mmc_softc *sc;
1165
1166 sc = device_get_softc(bus);
1167 switch (which) {
1168 default:
1169 return (EINVAL);
1170 case MMCBR_IVAR_BUS_MODE:
1171 sc->aw_host.ios.bus_mode = value;
1172 break;
1173 case MMCBR_IVAR_BUS_WIDTH:
1174 sc->aw_host.ios.bus_width = value;
1175 break;
1176 case MMCBR_IVAR_CHIP_SELECT:
1177 sc->aw_host.ios.chip_select = value;
1178 break;
1179 case MMCBR_IVAR_CLOCK:
1180 sc->aw_host.ios.clock = value;
1181 break;
1182 case MMCBR_IVAR_MODE:
1183 sc->aw_host.mode = value;
1184 break;
1185 case MMCBR_IVAR_OCR:
1186 sc->aw_host.ocr = value;
1187 break;
1188 case MMCBR_IVAR_POWER_MODE:
1189 sc->aw_host.ios.power_mode = value;
1190 break;
1191 case MMCBR_IVAR_VDD:
1192 sc->aw_host.ios.vdd = value;
1193 break;
1194 case MMCBR_IVAR_VCCQ:
1195 sc->aw_host.ios.vccq = value;
1196 break;
1197 case MMCBR_IVAR_TIMING:
1198 sc->aw_host.ios.timing = value;
1199 break;
1200 /* These are read-only */
1201 case MMCBR_IVAR_CAPS:
1202 case MMCBR_IVAR_HOST_OCR:
1203 case MMCBR_IVAR_F_MIN:
1204 case MMCBR_IVAR_F_MAX:
1205 case MMCBR_IVAR_MAX_DATA:
1206 return (EINVAL);
1207 }
1208
1209 return (0);
1210 }
1211
1212 static int
1213 aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon)
1214 {
1215 uint32_t reg;
1216 int retry;
1217
1218 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
1219 reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER |
1220 AW_MMC_CKCR_MASK_DATA0);
1221
1222 if (clkon)
1223 reg |= AW_MMC_CKCR_ENB;
1224 if (sc->aw_mmc_conf->mask_data0)
1225 reg |= AW_MMC_CKCR_MASK_DATA0;
1226
1227 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
1228
1229 reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK |
1230 AW_MMC_CMDR_WAIT_PRE_OVER;
1231 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg);
1232 retry = 0xfffff;
1233
1234 while (reg & AW_MMC_CMDR_LOAD && --retry > 0) {
1235 reg = AW_MMC_READ_4(sc, AW_MMC_CMDR);
1236 DELAY(10);
1237 }
1238 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
1239
1240 if (reg & AW_MMC_CMDR_LOAD) {
1241 device_printf(sc->aw_dev, "timeout updating clock\n");
1242 return (ETIMEDOUT);
1243 }
1244
1245 if (sc->aw_mmc_conf->mask_data0) {
1246 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
1247 reg &= ~AW_MMC_CKCR_MASK_DATA0;
1248 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
1249 }
1250
1251 return (0);
1252 }
1253
1254 #ifndef MMCCAM
1255 static int
1256 aw_mmc_switch_vccq(device_t bus, device_t child)
1257 {
1258 struct aw_mmc_softc *sc;
1259 int uvolt, err;
1260
1261 sc = device_get_softc(bus);
1262
1263 if (sc->mmc_helper.vqmmc_supply == NULL)
1264 return EOPNOTSUPP;
1265
1266 switch (sc->aw_host.ios.vccq) {
1267 case vccq_180:
1268 uvolt = 1800000;
1269 break;
1270 case vccq_330:
1271 uvolt = 3300000;
1272 break;
1273 default:
1274 return EINVAL;
1275 }
1276
1277 err = regulator_set_voltage(sc->mmc_helper.vqmmc_supply, uvolt, uvolt);
1278 if (err != 0) {
1279 device_printf(sc->aw_dev,
1280 "Cannot set vqmmc to %d<->%d\n",
1281 uvolt,
1282 uvolt);
1283 return (err);
1284 }
1285
1286 return (0);
1287 }
1288 #endif
1289
1290 static int
1291 aw_mmc_update_ios(device_t bus, device_t child)
1292 {
1293 int error;
1294 struct aw_mmc_softc *sc;
1295 struct mmc_ios *ios;
1296 unsigned int clock;
1297 uint32_t reg, div = 1;
1298 int reg_status;
1299 int rv;
1300
1301 sc = device_get_softc(bus);
1302
1303 ios = &sc->aw_host.ios;
1304
1305 /* Set the bus width. */
1306 switch (ios->bus_width) {
1307 case bus_width_1:
1308 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1);
1309 break;
1310 case bus_width_4:
1311 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4);
1312 break;
1313 case bus_width_8:
1314 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8);
1315 break;
1316 }
1317
1318 switch (ios->power_mode) {
1319 case power_on:
1320 break;
1321 case power_off:
1322 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD))
1323 device_printf(sc->aw_dev, "Powering down sd/mmc\n");
1324
1325 if (sc->mmc_helper.vmmc_supply) {
1326 rv = regulator_status(sc->mmc_helper.vmmc_supply, ®_status);
1327 if (rv == 0 && reg_status == REGULATOR_STATUS_ENABLED)
1328 regulator_disable(sc->mmc_helper.vmmc_supply);
1329 }
1330 if (sc->mmc_helper.vqmmc_supply) {
1331 rv = regulator_status(sc->mmc_helper.vqmmc_supply, ®_status);
1332 if (rv == 0 && reg_status == REGULATOR_STATUS_ENABLED)
1333 regulator_disable(sc->mmc_helper.vqmmc_supply);
1334 }
1335
1336 if (sc->mmc_helper.mmc_pwrseq)
1337 MMC_PWRSEQ_SET_POWER(sc->mmc_helper.mmc_pwrseq, false);
1338
1339 aw_mmc_reset(sc);
1340 break;
1341 case power_up:
1342 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD))
1343 device_printf(sc->aw_dev, "Powering up sd/mmc\n");
1344
1345 if (sc->mmc_helper.vmmc_supply) {
1346 rv = regulator_status(sc->mmc_helper.vmmc_supply, ®_status);
1347 if (rv == 0 && reg_status != REGULATOR_STATUS_ENABLED)
1348 regulator_enable(sc->mmc_helper.vmmc_supply);
1349 }
1350 if (sc->mmc_helper.vqmmc_supply) {
1351 rv = regulator_status(sc->mmc_helper.vqmmc_supply, ®_status);
1352 if (rv == 0 && reg_status != REGULATOR_STATUS_ENABLED)
1353 regulator_enable(sc->mmc_helper.vqmmc_supply);
1354 }
1355
1356 if (sc->mmc_helper.mmc_pwrseq)
1357 MMC_PWRSEQ_SET_POWER(sc->mmc_helper.mmc_pwrseq, true);
1358 aw_mmc_init(sc);
1359 break;
1360 };
1361
1362 /* Enable ddr mode if needed */
1363 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
1364 if (ios->timing == bus_timing_uhs_ddr50 ||
1365 ios->timing == bus_timing_mmc_ddr52)
1366 reg |= AW_MMC_GCTL_DDR_MOD_SEL;
1367 else
1368 reg &= ~AW_MMC_GCTL_DDR_MOD_SEL;
1369 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
1370
1371 if (ios->clock && ios->clock != sc->aw_clock) {
1372 sc->aw_clock = clock = ios->clock;
1373
1374 /* Disable clock */
1375 error = aw_mmc_update_clock(sc, 0);
1376 if (error != 0)
1377 return (error);
1378
1379 if (ios->timing == bus_timing_mmc_ddr52 &&
1380 (sc->aw_mmc_conf->new_timing ||
1381 ios->bus_width == bus_width_8)) {
1382 div = 2;
1383 clock <<= 1;
1384 }
1385
1386 /* Reset the divider. */
1387 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
1388 reg &= ~AW_MMC_CKCR_DIV;
1389 reg |= div - 1;
1390 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
1391
1392 /* New timing mode if needed */
1393 if (sc->aw_mmc_conf->new_timing) {
1394 reg = AW_MMC_READ_4(sc, AW_MMC_NTSR);
1395 reg |= AW_MMC_NTSR_MODE_SELECT;
1396 AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg);
1397 }
1398
1399 /* Set the MMC clock. */
1400 error = clk_disable(sc->aw_clk_mmc);
1401 if (error != 0 && bootverbose)
1402 device_printf(sc->aw_dev,
1403 "failed to disable mmc clock: %d\n", error);
1404 error = clk_set_freq(sc->aw_clk_mmc, clock,
1405 CLK_SET_ROUND_DOWN);
1406 if (error != 0) {
1407 device_printf(sc->aw_dev,
1408 "failed to set frequency to %u Hz: %d\n",
1409 clock, error);
1410 return (error);
1411 }
1412 error = clk_enable(sc->aw_clk_mmc);
1413 if (error != 0 && bootverbose)
1414 device_printf(sc->aw_dev,
1415 "failed to re-enable mmc clock: %d\n", error);
1416
1417 if (sc->aw_mmc_conf->can_calibrate)
1418 AW_MMC_WRITE_4(sc, AW_MMC_SAMP_DL, AW_MMC_SAMP_DL_SW_EN);
1419
1420 /* Enable clock. */
1421 error = aw_mmc_update_clock(sc, 1);
1422 if (error != 0)
1423 return (error);
1424 }
1425
1426 return (0);
1427 }
1428
1429 #ifndef MMCCAM
1430 static int
1431 aw_mmc_get_ro(device_t bus, device_t child)
1432 {
1433 struct aw_mmc_softc *sc;
1434
1435 sc = device_get_softc(bus);
1436
1437 return (mmc_fdt_gpio_get_readonly(&sc->mmc_helper));
1438 }
1439
1440 static int
1441 aw_mmc_acquire_host(device_t bus, device_t child)
1442 {
1443 struct aw_mmc_softc *sc;
1444 int error;
1445
1446 sc = device_get_softc(bus);
1447 AW_MMC_LOCK(sc);
1448 while (sc->aw_bus_busy) {
1449 error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0);
1450 if (error != 0) {
1451 AW_MMC_UNLOCK(sc);
1452 return (error);
1453 }
1454 }
1455 sc->aw_bus_busy++;
1456 AW_MMC_UNLOCK(sc);
1457
1458 return (0);
1459 }
1460
1461 static int
1462 aw_mmc_release_host(device_t bus, device_t child)
1463 {
1464 struct aw_mmc_softc *sc;
1465
1466 sc = device_get_softc(bus);
1467 AW_MMC_LOCK(sc);
1468 sc->aw_bus_busy--;
1469 wakeup(sc);
1470 AW_MMC_UNLOCK(sc);
1471
1472 return (0);
1473 }
1474 #endif
1475
1476 static device_method_t aw_mmc_methods[] = {
1477 /* Device interface */
1478 DEVMETHOD(device_probe, aw_mmc_probe),
1479 DEVMETHOD(device_attach, aw_mmc_attach),
1480 DEVMETHOD(device_detach, aw_mmc_detach),
1481
1482 /* Bus interface */
1483 DEVMETHOD(bus_read_ivar, aw_mmc_read_ivar),
1484 DEVMETHOD(bus_write_ivar, aw_mmc_write_ivar),
1485 DEVMETHOD(bus_add_child, bus_generic_add_child),
1486
1487 #ifndef MMCCAM
1488 /* MMC bridge interface */
1489 DEVMETHOD(mmcbr_update_ios, aw_mmc_update_ios),
1490 DEVMETHOD(mmcbr_request, aw_mmc_request),
1491 DEVMETHOD(mmcbr_get_ro, aw_mmc_get_ro),
1492 DEVMETHOD(mmcbr_switch_vccq, aw_mmc_switch_vccq),
1493 DEVMETHOD(mmcbr_acquire_host, aw_mmc_acquire_host),
1494 DEVMETHOD(mmcbr_release_host, aw_mmc_release_host),
1495 #endif
1496
1497 #ifdef MMCCAM
1498 /* MMCCAM interface */
1499 DEVMETHOD(mmc_sim_get_tran_settings, aw_mmc_get_tran_settings),
1500 DEVMETHOD(mmc_sim_set_tran_settings, aw_mmc_set_tran_settings),
1501 DEVMETHOD(mmc_sim_cam_request, aw_mmc_cam_request),
1502 DEVMETHOD(mmc_sim_cam_poll, aw_mmc_cam_poll),
1503 #endif
1504
1505 DEVMETHOD_END
1506 };
1507
1508 static driver_t aw_mmc_driver = {
1509 "aw_mmc",
1510 aw_mmc_methods,
1511 sizeof(struct aw_mmc_softc),
1512 };
1513
1514 DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, NULL, NULL);
1515 #ifndef MMCCAM
1516 MMC_DECLARE_BRIDGE(aw_mmc);
1517 #endif
1518 SIMPLEBUS_PNP_INFO(compat_data);
1519