1 /*-
2 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29 /* A10/A20 EMAC driver */
30
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/bus.h>
39 #include <sys/lock.h>
40 #include <sys/mbuf.h>
41 #include <sys/mutex.h>
42 #include <sys/rman.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
46 #include <sys/gpio.h>
47
48 #include <machine/bus.h>
49 #include <machine/resource.h>
50 #include <machine/intr.h>
51
52 #include <net/if.h>
53 #include <net/if_var.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/if_types.h>
58 #include <net/if_mib.h>
59 #include <net/ethernet.h>
60 #include <net/if_vlan_var.h>
61
62 #ifdef INET
63 #include <netinet/in.h>
64 #include <netinet/in_systm.h>
65 #include <netinet/in_var.h>
66 #include <netinet/ip.h>
67 #endif
68
69 #include <net/bpf.h>
70 #include <net/bpfdesc.h>
71
72 #include <dev/fdt/fdt_common.h>
73 #include <dev/ofw/ofw_bus.h>
74 #include <dev/ofw/ofw_bus_subr.h>
75
76 #include <dev/mii/mii.h>
77 #include <dev/mii/miivar.h>
78
79 #include <arm/allwinner/if_emacreg.h>
80 #include <arm/allwinner/aw_sid.h>
81
82 #include <dev/extres/clk/clk.h>
83
84 #include "miibus_if.h"
85
86 #include "gpio_if.h"
87
88 #include "a10_sramc.h"
89
90 struct emac_softc {
91 struct ifnet *emac_ifp;
92 device_t emac_dev;
93 device_t emac_miibus;
94 bus_space_handle_t emac_handle;
95 bus_space_tag_t emac_tag;
96 struct resource *emac_res;
97 struct resource *emac_irq;
98 void *emac_intrhand;
99 clk_t emac_clk;
100 int emac_if_flags;
101 struct mtx emac_mtx;
102 struct callout emac_tick_ch;
103 int emac_watchdog_timer;
104 int emac_rx_process_limit;
105 int emac_link;
106 uint32_t emac_fifo_mask;
107 };
108
109 static int emac_probe(device_t);
110 static int emac_attach(device_t);
111 static int emac_detach(device_t);
112 static int emac_shutdown(device_t);
113 static int emac_suspend(device_t);
114 static int emac_resume(device_t);
115
116 static int emac_sys_setup(struct emac_softc *);
117 static void emac_reset(struct emac_softc *);
118
119 static void emac_init_locked(struct emac_softc *);
120 static void emac_start_locked(struct ifnet *);
121 static void emac_init(void *);
122 static void emac_stop_locked(struct emac_softc *);
123 static void emac_intr(void *);
124 static int emac_ioctl(struct ifnet *, u_long, caddr_t);
125
126 static void emac_rxeof(struct emac_softc *, int);
127 static void emac_txeof(struct emac_softc *, uint32_t);
128
129 static int emac_miibus_readreg(device_t, int, int);
130 static int emac_miibus_writereg(device_t, int, int, int);
131 static void emac_miibus_statchg(device_t);
132
133 static int emac_ifmedia_upd(struct ifnet *);
134 static void emac_ifmedia_sts(struct ifnet *, struct ifmediareq *);
135
136 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
137 static int sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS);
138
139 #define EMAC_READ_REG(sc, reg) \
140 bus_space_read_4(sc->emac_tag, sc->emac_handle, reg)
141 #define EMAC_WRITE_REG(sc, reg, val) \
142 bus_space_write_4(sc->emac_tag, sc->emac_handle, reg, val)
143
144 static int
emac_sys_setup(struct emac_softc * sc)145 emac_sys_setup(struct emac_softc *sc)
146 {
147 int error;
148
149 /* Activate EMAC clock. */
150 error = clk_get_by_ofw_index(sc->emac_dev, 0, 0, &sc->emac_clk);
151 if (error != 0) {
152 device_printf(sc->emac_dev, "cannot get clock\n");
153 return (error);
154 }
155 error = clk_enable(sc->emac_clk);
156 if (error != 0) {
157 device_printf(sc->emac_dev, "cannot enable clock\n");
158 return (error);
159 }
160
161 /* Map sram. */
162 a10_map_to_emac();
163
164 return (0);
165 }
166
167 static void
emac_get_hwaddr(struct emac_softc * sc,uint8_t * hwaddr)168 emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr)
169 {
170 uint32_t val0, val1, rnd;
171 u_char rootkey[16];
172
173 /*
174 * Try to get MAC address from running hardware.
175 * If there is something non-zero there just use it.
176 *
177 * Otherwise set the address to a convenient locally assigned address,
178 * using the SID rootkey.
179 * This is was uboot does so we end up with the same mac as if uboot
180 * did set it.
181 * If we can't get the root key, generate a random one,
182 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
183 * assigned bit set, and the broadcast/multicast bit clear.
184 */
185 val0 = EMAC_READ_REG(sc, EMAC_MAC_A0);
186 val1 = EMAC_READ_REG(sc, EMAC_MAC_A1);
187 if ((val0 | val1) != 0 && (val0 | val1) != 0xffffff) {
188 hwaddr[0] = (val1 >> 16) & 0xff;
189 hwaddr[1] = (val1 >> 8) & 0xff;
190 hwaddr[2] = (val1 >> 0) & 0xff;
191 hwaddr[3] = (val0 >> 16) & 0xff;
192 hwaddr[4] = (val0 >> 8) & 0xff;
193 hwaddr[5] = (val0 >> 0) & 0xff;
194 } else {
195 if (aw_sid_get_rootkey(rootkey) == 0) {
196 hwaddr[0] = 0x2;
197 hwaddr[1] = rootkey[3];
198 hwaddr[2] = rootkey[12];
199 hwaddr[3] = rootkey[13];
200 hwaddr[4] = rootkey[14];
201 hwaddr[5] = rootkey[15];
202 }
203 else {
204 rnd = arc4random() & 0x00ffffff;
205 hwaddr[0] = 'b';
206 hwaddr[1] = 's';
207 hwaddr[2] = 'd';
208 hwaddr[3] = (rnd >> 16) & 0xff;
209 hwaddr[4] = (rnd >> 8) & 0xff;
210 hwaddr[5] = (rnd >> 0) & 0xff;
211 }
212 }
213 if (bootverbose)
214 printf("MAC address: %s\n", ether_sprintf(hwaddr));
215 }
216
217 static void
emac_set_rx_mode(struct emac_softc * sc)218 emac_set_rx_mode(struct emac_softc *sc)
219 {
220 struct ifnet *ifp;
221 struct ifmultiaddr *ifma;
222 uint32_t h, hashes[2];
223 uint32_t rcr = 0;
224
225 EMAC_ASSERT_LOCKED(sc);
226
227 ifp = sc->emac_ifp;
228
229 rcr = EMAC_READ_REG(sc, EMAC_RX_CTL);
230
231 /* Unicast packet and DA filtering */
232 rcr |= EMAC_RX_UCAD;
233 rcr |= EMAC_RX_DAF;
234
235 hashes[0] = 0;
236 hashes[1] = 0;
237 if (ifp->if_flags & IFF_ALLMULTI) {
238 hashes[0] = 0xffffffff;
239 hashes[1] = 0xffffffff;
240 } else {
241 if_maddr_rlock(ifp);
242 TAILQ_FOREACH(ifma, &sc->emac_ifp->if_multiaddrs, ifma_link) {
243 if (ifma->ifma_addr->sa_family != AF_LINK)
244 continue;
245 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
246 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
247 hashes[h >> 5] |= 1 << (h & 0x1f);
248 }
249 if_maddr_runlock(ifp);
250 }
251 rcr |= EMAC_RX_MCO;
252 rcr |= EMAC_RX_MHF;
253 EMAC_WRITE_REG(sc, EMAC_RX_HASH0, hashes[0]);
254 EMAC_WRITE_REG(sc, EMAC_RX_HASH1, hashes[1]);
255
256 if (ifp->if_flags & IFF_BROADCAST) {
257 rcr |= EMAC_RX_BCO;
258 rcr |= EMAC_RX_MCO;
259 }
260
261 if (ifp->if_flags & IFF_PROMISC)
262 rcr |= EMAC_RX_PA;
263 else
264 rcr |= EMAC_RX_UCAD;
265
266 EMAC_WRITE_REG(sc, EMAC_RX_CTL, rcr);
267 }
268
269 static void
emac_reset(struct emac_softc * sc)270 emac_reset(struct emac_softc *sc)
271 {
272
273 EMAC_WRITE_REG(sc, EMAC_CTL, 0);
274 DELAY(200);
275 EMAC_WRITE_REG(sc, EMAC_CTL, 1);
276 DELAY(200);
277 }
278
279 static void
emac_drain_rxfifo(struct emac_softc * sc)280 emac_drain_rxfifo(struct emac_softc *sc)
281 {
282 uint32_t data;
283
284 while (EMAC_READ_REG(sc, EMAC_RX_FBC) > 0)
285 data = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
286 }
287
288 static void
emac_txeof(struct emac_softc * sc,uint32_t status)289 emac_txeof(struct emac_softc *sc, uint32_t status)
290 {
291 struct ifnet *ifp;
292
293 EMAC_ASSERT_LOCKED(sc);
294
295 ifp = sc->emac_ifp;
296 status &= (EMAC_TX_FIFO0 | EMAC_TX_FIFO1);
297 sc->emac_fifo_mask &= ~status;
298 if (status == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
299 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 2);
300 else
301 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
302 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
303
304 /* Unarm watchdog timer if no TX */
305 sc->emac_watchdog_timer = 0;
306 }
307
308 static void
emac_rxeof(struct emac_softc * sc,int count)309 emac_rxeof(struct emac_softc *sc, int count)
310 {
311 struct ifnet *ifp;
312 struct mbuf *m, *m0;
313 uint32_t reg_val, rxcount;
314 int16_t len;
315 uint16_t status;
316 int i;
317
318 ifp = sc->emac_ifp;
319 for (; count > 0 &&
320 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; count--) {
321 /*
322 * Race warning: The first packet might arrive with
323 * the interrupts disabled, but the second will fix
324 */
325 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC);
326 if (!rxcount) {
327 /* Had one stuck? */
328 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC);
329 if (!rxcount)
330 return;
331 }
332 /* Check packet header */
333 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
334 if (reg_val != EMAC_PACKET_HEADER) {
335 /* Packet header is wrong */
336 if (bootverbose)
337 if_printf(ifp, "wrong packet header\n");
338 /* Disable RX */
339 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
340 reg_val &= ~EMAC_CTL_RX_EN;
341 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
342
343 /* Flush RX FIFO */
344 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
345 reg_val |= EMAC_RX_FLUSH_FIFO;
346 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
347 for (i = 100; i > 0; i--) {
348 DELAY(100);
349 if ((EMAC_READ_REG(sc, EMAC_RX_CTL) &
350 EMAC_RX_FLUSH_FIFO) == 0)
351 break;
352 }
353 if (i == 0) {
354 device_printf(sc->emac_dev,
355 "flush FIFO timeout\n");
356 /* Reinitialize controller */
357 emac_init_locked(sc);
358 return;
359 }
360 /* Enable RX */
361 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
362 reg_val |= EMAC_CTL_RX_EN;
363 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
364
365 return;
366 }
367
368 /* Get packet size and status */
369 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
370 len = reg_val & 0xffff;
371 status = (reg_val >> 16) & 0xffff;
372
373 if (len < 64 || (status & EMAC_PKT_OK) == 0) {
374 if (bootverbose)
375 if_printf(ifp,
376 "bad packet: len = %i status = %i\n",
377 len, status);
378 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
379 emac_drain_rxfifo(sc);
380 continue;
381 }
382 #if 0
383 if (status & (EMAC_CRCERR | EMAC_LENERR)) {
384 good_packet = 0;
385 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
386 if (status & EMAC_CRCERR)
387 if_printf(ifp, "crc error\n");
388 if (status & EMAC_LENERR)
389 if_printf(ifp, "length error\n");
390 }
391 #endif
392 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
393 if (m == NULL) {
394 emac_drain_rxfifo(sc);
395 return;
396 }
397 m->m_len = m->m_pkthdr.len = MCLBYTES;
398
399 /* Copy entire frame to mbuf first. */
400 bus_space_read_multi_4(sc->emac_tag, sc->emac_handle,
401 EMAC_RX_IO_DATA, mtod(m, uint32_t *), roundup2(len, 4) / 4);
402
403 m->m_pkthdr.rcvif = ifp;
404 m->m_len = m->m_pkthdr.len = len - ETHER_CRC_LEN;
405
406 /*
407 * Emac controller needs strict aligment, so to avoid
408 * copying over an entire frame to align, we allocate
409 * a new mbuf and copy ethernet header + IP header to
410 * the new mbuf. The new mbuf is prepended into the
411 * existing mbuf chain.
412 */
413 if (m->m_len <= (MHLEN - ETHER_HDR_LEN)) {
414 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
415 m->m_data += ETHER_HDR_LEN;
416 } else if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN) &&
417 m->m_len > (MHLEN - ETHER_HDR_LEN)) {
418 MGETHDR(m0, M_NOWAIT, MT_DATA);
419 if (m0 != NULL) {
420 len = ETHER_HDR_LEN + m->m_pkthdr.l2hlen;
421 bcopy(m->m_data, m0->m_data, len);
422 m->m_data += len;
423 m->m_len -= len;
424 m0->m_len = len;
425 M_MOVE_PKTHDR(m0, m);
426 m0->m_next = m;
427 m = m0;
428 } else {
429 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
430 m_freem(m);
431 m = NULL;
432 continue;
433 }
434 } else if (m->m_len > EMAC_MAC_MAXF) {
435 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
436 m_freem(m);
437 m = NULL;
438 continue;
439 }
440 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
441 EMAC_UNLOCK(sc);
442 (*ifp->if_input)(ifp, m);
443 EMAC_LOCK(sc);
444 }
445 }
446
447 static void
emac_watchdog(struct emac_softc * sc)448 emac_watchdog(struct emac_softc *sc)
449 {
450 struct ifnet *ifp;
451
452 EMAC_ASSERT_LOCKED(sc);
453
454 if (sc->emac_watchdog_timer == 0 || --sc->emac_watchdog_timer)
455 return;
456
457 ifp = sc->emac_ifp;
458
459 if (sc->emac_link == 0) {
460 if (bootverbose)
461 if_printf(sc->emac_ifp, "watchdog timeout "
462 "(missed link)\n");
463 } else
464 if_printf(sc->emac_ifp, "watchdog timeout -- resetting\n");
465
466 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
467 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
468 emac_init_locked(sc);
469 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
470 emac_start_locked(ifp);
471 }
472
473 static void
emac_tick(void * arg)474 emac_tick(void *arg)
475 {
476 struct emac_softc *sc;
477 struct mii_data *mii;
478
479 sc = (struct emac_softc *)arg;
480 mii = device_get_softc(sc->emac_miibus);
481 mii_tick(mii);
482
483 emac_watchdog(sc);
484 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
485 }
486
487 static void
emac_init(void * xcs)488 emac_init(void *xcs)
489 {
490 struct emac_softc *sc;
491
492 sc = (struct emac_softc *)xcs;
493 EMAC_LOCK(sc);
494 emac_init_locked(sc);
495 EMAC_UNLOCK(sc);
496 }
497
498 static void
emac_init_locked(struct emac_softc * sc)499 emac_init_locked(struct emac_softc *sc)
500 {
501 struct ifnet *ifp;
502 struct mii_data *mii;
503 uint32_t reg_val;
504 uint8_t *eaddr;
505
506 EMAC_ASSERT_LOCKED(sc);
507
508 ifp = sc->emac_ifp;
509 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
510 return;
511
512 /* Flush RX FIFO */
513 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
514 reg_val |= EMAC_RX_FLUSH_FIFO;
515 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
516 DELAY(1);
517
518 /* Soft reset MAC */
519 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0);
520 reg_val &= (~EMAC_MAC_CTL0_SOFT_RST);
521 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
522
523 /* Set MII clock */
524 reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG);
525 reg_val &= (~(0xf << 2));
526 reg_val |= (0xd << 2);
527 EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val);
528
529 /* Clear RX counter */
530 EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0);
531
532 /* Disable all interrupt and clear interrupt status */
533 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
534 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
535 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
536 DELAY(1);
537
538 /* Set up TX */
539 reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE);
540 reg_val |= EMAC_TX_AB_M;
541 reg_val &= EMAC_TX_TM;
542 EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val);
543
544 /* Set up RX */
545 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
546 reg_val |= EMAC_RX_SETUP;
547 reg_val &= EMAC_RX_TM;
548 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
549
550 /* Set up MAC CTL0. */
551 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0);
552 reg_val |= EMAC_MAC_CTL0_SETUP;
553 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
554
555 /* Set up MAC CTL1. */
556 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL1);
557 reg_val |= EMAC_MAC_CTL1_SETUP;
558 EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val);
559
560 /* Set up IPGT */
561 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, EMAC_MAC_IPGT_FD);
562
563 /* Set up IPGR */
564 EMAC_WRITE_REG(sc, EMAC_MAC_IPGR, EMAC_MAC_NBTB_IPG2 |
565 (EMAC_MAC_NBTB_IPG1 << 8));
566
567 /* Set up Collison window */
568 EMAC_WRITE_REG(sc, EMAC_MAC_CLRT, EMAC_MAC_RM | (EMAC_MAC_CW << 8));
569
570 /* Set up Max Frame Length */
571 EMAC_WRITE_REG(sc, EMAC_MAC_MAXF, EMAC_MAC_MFL);
572
573 /* Setup ethernet address */
574 eaddr = IF_LLADDR(ifp);
575 EMAC_WRITE_REG(sc, EMAC_MAC_A1, eaddr[0] << 16 |
576 eaddr[1] << 8 | eaddr[2]);
577 EMAC_WRITE_REG(sc, EMAC_MAC_A0, eaddr[3] << 16 |
578 eaddr[4] << 8 | eaddr[5]);
579
580 /* Setup rx filter */
581 emac_set_rx_mode(sc);
582
583 /* Enable RX/TX0/RX Hlevel interrupt */
584 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL);
585 reg_val |= EMAC_INT_EN;
586 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);
587
588 ifp->if_drv_flags |= IFF_DRV_RUNNING;
589 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
590
591 sc->emac_link = 0;
592
593 /* Switch to the current media. */
594 mii = device_get_softc(sc->emac_miibus);
595 mii_mediachg(mii);
596
597 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
598 }
599
600
601 static void
emac_start(struct ifnet * ifp)602 emac_start(struct ifnet *ifp)
603 {
604 struct emac_softc *sc;
605
606 sc = ifp->if_softc;
607 EMAC_LOCK(sc);
608 emac_start_locked(ifp);
609 EMAC_UNLOCK(sc);
610 }
611
612 static void
emac_start_locked(struct ifnet * ifp)613 emac_start_locked(struct ifnet *ifp)
614 {
615 struct emac_softc *sc;
616 struct mbuf *m, *m0;
617 uint32_t fifo, reg;
618
619 sc = ifp->if_softc;
620 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
621 return;
622 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
623 return;
624 if (sc->emac_link == 0)
625 return;
626 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
627 if (m == NULL)
628 return;
629
630 /* Select channel */
631 if (sc->emac_fifo_mask & EMAC_TX_FIFO0)
632 fifo = 1;
633 else
634 fifo = 0;
635 sc->emac_fifo_mask |= (1 << fifo);
636 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
637 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
638 EMAC_WRITE_REG(sc, EMAC_TX_INS, fifo);
639
640 /*
641 * Emac controller wants 4 byte aligned TX buffers.
642 * We have to copy pretty much all the time.
643 */
644 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0) {
645 m0 = m_defrag(m, M_NOWAIT);
646 if (m0 == NULL) {
647 m_freem(m);
648 m = NULL;
649 return;
650 }
651 m = m0;
652 }
653 /* Write data */
654 bus_space_write_multi_4(sc->emac_tag, sc->emac_handle,
655 EMAC_TX_IO_DATA, mtod(m, uint32_t *),
656 roundup2(m->m_len, 4) / 4);
657
658 /* Send the data lengh. */
659 reg = (fifo == 0) ? EMAC_TX_PL0 : EMAC_TX_PL1;
660 EMAC_WRITE_REG(sc, reg, m->m_len);
661
662 /* Start translate from fifo to phy. */
663 reg = (fifo == 0) ? EMAC_TX_CTL0 : EMAC_TX_CTL1;
664 EMAC_WRITE_REG(sc, reg, EMAC_READ_REG(sc, reg) | 1);
665
666 /* Set timeout */
667 sc->emac_watchdog_timer = 5;
668
669 /* Data have been sent to hardware, it is okay to free the mbuf now. */
670 BPF_MTAP(ifp, m);
671 m_freem(m);
672 }
673
674 static void
emac_stop_locked(struct emac_softc * sc)675 emac_stop_locked(struct emac_softc *sc)
676 {
677 struct ifnet *ifp;
678 uint32_t reg_val;
679
680 EMAC_ASSERT_LOCKED(sc);
681
682 ifp = sc->emac_ifp;
683 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
684 sc->emac_link = 0;
685
686 /* Disable all interrupt and clear interrupt status */
687 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
688 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
689 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
690
691 /* Disable RX/TX */
692 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
693 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN);
694 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
695
696 callout_stop(&sc->emac_tick_ch);
697 }
698
699 static void
emac_intr(void * arg)700 emac_intr(void *arg)
701 {
702 struct emac_softc *sc;
703 struct ifnet *ifp;
704 uint32_t reg_val;
705
706 sc = (struct emac_softc *)arg;
707 EMAC_LOCK(sc);
708
709 /* Disable all interrupts */
710 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
711 /* Get EMAC interrupt status */
712 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
713 /* Clear ISR status */
714 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
715
716 /* Received incoming packet */
717 if (reg_val & EMAC_INT_STA_RX)
718 emac_rxeof(sc, sc->emac_rx_process_limit);
719
720 /* Transmit Interrupt check */
721 if (reg_val & EMAC_INT_STA_TX) {
722 emac_txeof(sc, reg_val);
723 ifp = sc->emac_ifp;
724 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
725 emac_start_locked(ifp);
726 }
727
728 /* Re-enable interrupt mask */
729 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL);
730 reg_val |= EMAC_INT_EN;
731 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);
732 EMAC_UNLOCK(sc);
733 }
734
735 static int
emac_ioctl(struct ifnet * ifp,u_long command,caddr_t data)736 emac_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
737 {
738 struct emac_softc *sc;
739 struct mii_data *mii;
740 struct ifreq *ifr;
741 int error = 0;
742
743 sc = ifp->if_softc;
744 ifr = (struct ifreq *)data;
745
746 switch (command) {
747 case SIOCSIFFLAGS:
748 EMAC_LOCK(sc);
749 if (ifp->if_flags & IFF_UP) {
750 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
751 if ((ifp->if_flags ^ sc->emac_if_flags) &
752 (IFF_PROMISC | IFF_ALLMULTI))
753 emac_set_rx_mode(sc);
754 } else
755 emac_init_locked(sc);
756 } else {
757 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
758 emac_stop_locked(sc);
759 }
760 sc->emac_if_flags = ifp->if_flags;
761 EMAC_UNLOCK(sc);
762 break;
763 case SIOCADDMULTI:
764 case SIOCDELMULTI:
765 EMAC_LOCK(sc);
766 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
767 emac_set_rx_mode(sc);
768 }
769 EMAC_UNLOCK(sc);
770 break;
771 case SIOCGIFMEDIA:
772 case SIOCSIFMEDIA:
773 mii = device_get_softc(sc->emac_miibus);
774 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
775 break;
776 default:
777 error = ether_ioctl(ifp, command, data);
778 break;
779 }
780 return (error);
781 }
782
783 static int
emac_probe(device_t dev)784 emac_probe(device_t dev)
785 {
786
787 if (!ofw_bus_status_okay(dev))
788 return (ENXIO);
789
790 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-emac"))
791 return (ENXIO);
792
793 device_set_desc(dev, "A10/A20 EMAC ethernet controller");
794 return (BUS_PROBE_DEFAULT);
795 }
796
797 static int
emac_detach(device_t dev)798 emac_detach(device_t dev)
799 {
800 struct emac_softc *sc;
801
802 sc = device_get_softc(dev);
803 sc->emac_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
804 if (device_is_attached(dev)) {
805 ether_ifdetach(sc->emac_ifp);
806 EMAC_LOCK(sc);
807 emac_stop_locked(sc);
808 EMAC_UNLOCK(sc);
809 callout_drain(&sc->emac_tick_ch);
810 }
811
812 if (sc->emac_intrhand != NULL)
813 bus_teardown_intr(sc->emac_dev, sc->emac_irq,
814 sc->emac_intrhand);
815
816 if (sc->emac_miibus != NULL) {
817 device_delete_child(sc->emac_dev, sc->emac_miibus);
818 bus_generic_detach(sc->emac_dev);
819 }
820
821 if (sc->emac_clk != NULL)
822 clk_disable(sc->emac_clk);
823
824 if (sc->emac_res != NULL)
825 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->emac_res);
826
827 if (sc->emac_irq != NULL)
828 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->emac_irq);
829
830 if (sc->emac_ifp != NULL)
831 if_free(sc->emac_ifp);
832
833 if (mtx_initialized(&sc->emac_mtx))
834 mtx_destroy(&sc->emac_mtx);
835
836 return (0);
837 }
838
839 static int
emac_shutdown(device_t dev)840 emac_shutdown(device_t dev)
841 {
842
843 return (emac_suspend(dev));
844 }
845
846 static int
emac_suspend(device_t dev)847 emac_suspend(device_t dev)
848 {
849 struct emac_softc *sc;
850 struct ifnet *ifp;
851
852 sc = device_get_softc(dev);
853
854 EMAC_LOCK(sc);
855 ifp = sc->emac_ifp;
856 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
857 emac_stop_locked(sc);
858 EMAC_UNLOCK(sc);
859
860 return (0);
861 }
862
863 static int
emac_resume(device_t dev)864 emac_resume(device_t dev)
865 {
866 struct emac_softc *sc;
867 struct ifnet *ifp;
868
869 sc = device_get_softc(dev);
870
871 EMAC_LOCK(sc);
872 ifp = sc->emac_ifp;
873 if ((ifp->if_flags & IFF_UP) != 0) {
874 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
875 emac_init_locked(sc);
876 }
877 EMAC_UNLOCK(sc);
878
879 return (0);
880 }
881
882 static int
emac_attach(device_t dev)883 emac_attach(device_t dev)
884 {
885 struct emac_softc *sc;
886 struct ifnet *ifp;
887 int error, rid;
888 uint8_t eaddr[ETHER_ADDR_LEN];
889
890 sc = device_get_softc(dev);
891 sc->emac_dev = dev;
892
893 error = 0;
894 mtx_init(&sc->emac_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
895 MTX_DEF);
896 callout_init_mtx(&sc->emac_tick_ch, &sc->emac_mtx, 0);
897
898 rid = 0;
899 sc->emac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
900 RF_ACTIVE);
901 if (sc->emac_res == NULL) {
902 device_printf(dev, "unable to map memory\n");
903 error = ENXIO;
904 goto fail;
905 }
906
907 sc->emac_tag = rman_get_bustag(sc->emac_res);
908 sc->emac_handle = rman_get_bushandle(sc->emac_res);
909
910 rid = 0;
911 sc->emac_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
912 RF_SHAREABLE | RF_ACTIVE);
913 if (sc->emac_irq == NULL) {
914 device_printf(dev, "cannot allocate IRQ resources.\n");
915 error = ENXIO;
916 goto fail;
917 }
918 /* Create device sysctl node. */
919 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
920 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
921 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW,
922 &sc->emac_rx_process_limit, 0, sysctl_hw_emac_proc_limit, "I",
923 "max number of Rx events to process");
924
925 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT;
926 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
927 "process_limit", &sc->emac_rx_process_limit);
928 if (error == 0) {
929 if (sc->emac_rx_process_limit < EMAC_PROC_MIN ||
930 sc->emac_rx_process_limit > EMAC_PROC_MAX) {
931 device_printf(dev, "process_limit value out of range; "
932 "using default: %d\n", EMAC_PROC_DEFAULT);
933 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT;
934 }
935 }
936 /* Setup EMAC */
937 error = emac_sys_setup(sc);
938 if (error != 0)
939 goto fail;
940
941 emac_reset(sc);
942
943 ifp = sc->emac_ifp = if_alloc(IFT_ETHER);
944 if (ifp == NULL) {
945 device_printf(dev, "unable to allocate ifp\n");
946 error = ENOSPC;
947 goto fail;
948 }
949 ifp->if_softc = sc;
950
951 /* Setup MII */
952 error = mii_attach(dev, &sc->emac_miibus, ifp, emac_ifmedia_upd,
953 emac_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
954 if (error != 0) {
955 device_printf(dev, "PHY probe failed\n");
956 goto fail;
957 }
958
959 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
960 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
961 ifp->if_start = emac_start;
962 ifp->if_ioctl = emac_ioctl;
963 ifp->if_init = emac_init;
964 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
965
966 /* Get MAC address */
967 emac_get_hwaddr(sc, eaddr);
968 ether_ifattach(ifp, eaddr);
969
970 /* VLAN capability setup. */
971 ifp->if_capabilities |= IFCAP_VLAN_MTU;
972 ifp->if_capenable = ifp->if_capabilities;
973 /* Tell the upper layer we support VLAN over-sized frames. */
974 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
975
976 error = bus_setup_intr(dev, sc->emac_irq, INTR_TYPE_NET | INTR_MPSAFE,
977 NULL, emac_intr, sc, &sc->emac_intrhand);
978 if (error != 0) {
979 device_printf(dev, "could not set up interrupt handler.\n");
980 ether_ifdetach(ifp);
981 goto fail;
982 }
983
984 fail:
985 if (error != 0)
986 emac_detach(dev);
987 return (error);
988 }
989
990 static boolean_t
emac_miibus_iowait(struct emac_softc * sc)991 emac_miibus_iowait(struct emac_softc *sc)
992 {
993 uint32_t timeout;
994
995 for (timeout = 100; timeout != 0; --timeout) {
996 DELAY(100);
997 if ((EMAC_READ_REG(sc, EMAC_MAC_MIND) & 0x1) == 0)
998 return (true);
999 }
1000
1001 return (false);
1002 }
1003
1004 /*
1005 * The MII bus interface
1006 */
1007 static int
emac_miibus_readreg(device_t dev,int phy,int reg)1008 emac_miibus_readreg(device_t dev, int phy, int reg)
1009 {
1010 struct emac_softc *sc;
1011 int rval;
1012
1013 sc = device_get_softc(dev);
1014
1015 /* Issue phy address and reg */
1016 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
1017 /* Pull up the phy io line */
1018 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1);
1019 if (!emac_miibus_iowait(sc)) {
1020 device_printf(dev, "timeout waiting for mii read\n");
1021 return (0);
1022 }
1023 /* Push down the phy io line */
1024 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0);
1025 /* Read data */
1026 rval = EMAC_READ_REG(sc, EMAC_MAC_MRDD);
1027
1028 return (rval);
1029 }
1030
1031 static int
emac_miibus_writereg(device_t dev,int phy,int reg,int data)1032 emac_miibus_writereg(device_t dev, int phy, int reg, int data)
1033 {
1034 struct emac_softc *sc;
1035
1036 sc = device_get_softc(dev);
1037
1038 /* Issue phy address and reg */
1039 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
1040 /* Write data */
1041 EMAC_WRITE_REG(sc, EMAC_MAC_MWTD, data);
1042 /* Pull up the phy io line */
1043 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1);
1044 if (!emac_miibus_iowait(sc)) {
1045 device_printf(dev, "timeout waiting for mii write\n");
1046 return (0);
1047 }
1048 /* Push down the phy io line */
1049 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0);
1050
1051 return (0);
1052 }
1053
1054 static void
emac_miibus_statchg(device_t dev)1055 emac_miibus_statchg(device_t dev)
1056 {
1057 struct emac_softc *sc;
1058 struct mii_data *mii;
1059 struct ifnet *ifp;
1060 uint32_t reg_val;
1061
1062 sc = device_get_softc(dev);
1063
1064 mii = device_get_softc(sc->emac_miibus);
1065 ifp = sc->emac_ifp;
1066 if (mii == NULL || ifp == NULL ||
1067 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1068 return;
1069
1070 sc->emac_link = 0;
1071 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1072 (IFM_ACTIVE | IFM_AVALID)) {
1073 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1074 case IFM_10_T:
1075 case IFM_100_TX:
1076 sc->emac_link = 1;
1077 break;
1078 default:
1079 break;
1080 }
1081 }
1082 /* Program MACs with resolved speed/duplex. */
1083 if (sc->emac_link != 0) {
1084 reg_val = EMAC_READ_REG(sc, EMAC_MAC_IPGT);
1085 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1086 reg_val &= ~EMAC_MAC_IPGT_HD;
1087 reg_val |= EMAC_MAC_IPGT_FD;
1088 } else {
1089 reg_val &= ~EMAC_MAC_IPGT_FD;
1090 reg_val |= EMAC_MAC_IPGT_HD;
1091 }
1092 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val);
1093 /* Enable RX/TX */
1094 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
1095 reg_val |= EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN;
1096 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
1097 } else {
1098 /* Disable RX/TX */
1099 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
1100 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN);
1101 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
1102 }
1103 }
1104
1105 static int
emac_ifmedia_upd(struct ifnet * ifp)1106 emac_ifmedia_upd(struct ifnet *ifp)
1107 {
1108 struct emac_softc *sc;
1109 struct mii_data *mii;
1110 struct mii_softc *miisc;
1111 int error;
1112
1113 sc = ifp->if_softc;
1114 mii = device_get_softc(sc->emac_miibus);
1115 EMAC_LOCK(sc);
1116 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1117 PHY_RESET(miisc);
1118 error = mii_mediachg(mii);
1119 EMAC_UNLOCK(sc);
1120
1121 return (error);
1122 }
1123
1124 static void
emac_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1125 emac_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1126 {
1127 struct emac_softc *sc;
1128 struct mii_data *mii;
1129
1130 sc = ifp->if_softc;
1131 mii = device_get_softc(sc->emac_miibus);
1132
1133 EMAC_LOCK(sc);
1134 mii_pollstat(mii);
1135 ifmr->ifm_active = mii->mii_media_active;
1136 ifmr->ifm_status = mii->mii_media_status;
1137 EMAC_UNLOCK(sc);
1138 }
1139
1140 static device_method_t emac_methods[] = {
1141 /* Device interface */
1142 DEVMETHOD(device_probe, emac_probe),
1143 DEVMETHOD(device_attach, emac_attach),
1144 DEVMETHOD(device_detach, emac_detach),
1145 DEVMETHOD(device_shutdown, emac_shutdown),
1146 DEVMETHOD(device_suspend, emac_suspend),
1147 DEVMETHOD(device_resume, emac_resume),
1148
1149 /* bus interface, for miibus */
1150 DEVMETHOD(bus_print_child, bus_generic_print_child),
1151 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1152
1153 /* MII interface */
1154 DEVMETHOD(miibus_readreg, emac_miibus_readreg),
1155 DEVMETHOD(miibus_writereg, emac_miibus_writereg),
1156 DEVMETHOD(miibus_statchg, emac_miibus_statchg),
1157
1158 DEVMETHOD_END
1159 };
1160
1161 static driver_t emac_driver = {
1162 "emac",
1163 emac_methods,
1164 sizeof(struct emac_softc)
1165 };
1166
1167 static devclass_t emac_devclass;
1168
1169 DRIVER_MODULE(emac, simplebus, emac_driver, emac_devclass, 0, 0);
1170 DRIVER_MODULE(miibus, emac, miibus_driver, miibus_devclass, 0, 0);
1171 MODULE_DEPEND(emac, miibus, 1, 1, 1);
1172 MODULE_DEPEND(emac, ether, 1, 1, 1);
1173
1174 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)1175 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
1176 {
1177 int error, value;
1178
1179 if (arg1 == NULL)
1180 return (EINVAL);
1181 value = *(int *)arg1;
1182 error = sysctl_handle_int(oidp, &value, 0, req);
1183 if (error || req->newptr == NULL)
1184 return (error);
1185 if (value < low || value > high)
1186 return (EINVAL);
1187 *(int *)arg1 = value;
1188
1189 return (0);
1190 }
1191
1192 static int
sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS)1193 sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS)
1194 {
1195
1196 return (sysctl_int_range(oidp, arg1, arg2, req,
1197 EMAC_PROC_MIN, EMAC_PROC_MAX));
1198 }
1199