1 /*-
2 * Copyright (c) 2013-2015 Sandvine Inc. All rights reserved.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include "opt_bus.h"
31
32 #include <sys/param.h>
33 #include <sys/conf.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/fcntl.h>
38 #include <sys/ioccom.h>
39 #include <sys/iov.h>
40 #include <sys/linker.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <sys/pciio.h>
44 #include <sys/queue.h>
45 #include <sys/rman.h>
46 #include <sys/sysctl.h>
47
48 #include <machine/bus.h>
49 #include <machine/stdarg.h>
50
51 #include <sys/nv.h>
52 #include <sys/iov_schema.h>
53
54 #include <dev/pci/pcireg.h>
55 #include <dev/pci/pcivar.h>
56 #include <dev/pci/pci_iov.h>
57 #include <dev/pci/pci_private.h>
58 #include <dev/pci/pci_iov_private.h>
59 #include <dev/pci/schema_private.h>
60
61 #include "pcib_if.h"
62
63 static MALLOC_DEFINE(M_SRIOV, "sr_iov", "PCI SR-IOV allocations");
64
65 static d_ioctl_t pci_iov_ioctl;
66
67 static struct cdevsw iov_cdevsw = {
68 .d_version = D_VERSION,
69 .d_name = "iov",
70 .d_ioctl = pci_iov_ioctl
71 };
72
73 SYSCTL_DECL(_hw_pci);
74
75 /*
76 * The maximum amount of memory we will allocate for user configuration of an
77 * SR-IOV device. 1MB ought to be enough for anyone, but leave this
78 * configurable just in case.
79 */
80 static u_long pci_iov_max_config = 1024 * 1024;
81 SYSCTL_ULONG(_hw_pci, OID_AUTO, iov_max_config, CTLFLAG_RWTUN,
82 &pci_iov_max_config, 0, "Maximum allowed size of SR-IOV configuration.");
83
84
85 #define IOV_READ(d, r, w) \
86 pci_read_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, w)
87
88 #define IOV_WRITE(d, r, v, w) \
89 pci_write_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, v, w)
90
91 static nvlist_t *pci_iov_build_schema(nvlist_t **pf_schema,
92 nvlist_t **vf_schema);
93 static void pci_iov_build_pf_schema(nvlist_t *schema,
94 nvlist_t **driver_schema);
95 static void pci_iov_build_vf_schema(nvlist_t *schema,
96 nvlist_t **driver_schema);
97 static nvlist_t *pci_iov_get_pf_subsystem_schema(void);
98 static nvlist_t *pci_iov_get_vf_subsystem_schema(void);
99
100 int
pci_iov_attach_method(device_t bus,device_t dev,nvlist_t * pf_schema,nvlist_t * vf_schema)101 pci_iov_attach_method(device_t bus, device_t dev, nvlist_t *pf_schema,
102 nvlist_t *vf_schema)
103 {
104 device_t pcib;
105 struct pci_devinfo *dinfo;
106 struct pcicfg_iov *iov;
107 nvlist_t *schema;
108 uint32_t version;
109 int error;
110 int iov_pos;
111
112 dinfo = device_get_ivars(dev);
113 pcib = device_get_parent(bus);
114 schema = NULL;
115
116 error = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos);
117
118 if (error != 0)
119 return (error);
120
121 version = pci_read_config(dev, iov_pos, 4);
122 if (PCI_EXTCAP_VER(version) != 1) {
123 if (bootverbose)
124 device_printf(dev,
125 "Unsupported version of SR-IOV (%d) detected\n",
126 PCI_EXTCAP_VER(version));
127
128 return (ENXIO);
129 }
130
131 iov = malloc(sizeof(*dinfo->cfg.iov), M_SRIOV, M_WAITOK | M_ZERO);
132
133 mtx_lock(&Giant);
134 if (dinfo->cfg.iov != NULL) {
135 error = EBUSY;
136 goto cleanup;
137 }
138 iov->iov_pos = iov_pos;
139
140 schema = pci_iov_build_schema(&pf_schema, &vf_schema);
141 if (schema == NULL) {
142 error = ENOMEM;
143 goto cleanup;
144 }
145
146 error = pci_iov_validate_schema(schema);
147 if (error != 0)
148 goto cleanup;
149 iov->iov_schema = schema;
150
151 iov->iov_cdev = make_dev(&iov_cdevsw, device_get_unit(dev),
152 UID_ROOT, GID_WHEEL, 0600, "iov/%s", device_get_nameunit(dev));
153
154 if (iov->iov_cdev == NULL) {
155 error = ENOMEM;
156 goto cleanup;
157 }
158
159 dinfo->cfg.iov = iov;
160 iov->iov_cdev->si_drv1 = dinfo;
161 mtx_unlock(&Giant);
162
163 return (0);
164
165 cleanup:
166 nvlist_destroy(schema);
167 nvlist_destroy(pf_schema);
168 nvlist_destroy(vf_schema);
169 free(iov, M_SRIOV);
170 mtx_unlock(&Giant);
171 return (error);
172 }
173
174 int
pci_iov_detach_method(device_t bus,device_t dev)175 pci_iov_detach_method(device_t bus, device_t dev)
176 {
177 struct pci_devinfo *dinfo;
178 struct pcicfg_iov *iov;
179
180 mtx_lock(&Giant);
181 dinfo = device_get_ivars(dev);
182 iov = dinfo->cfg.iov;
183
184 if (iov == NULL) {
185 mtx_unlock(&Giant);
186 return (0);
187 }
188
189 if (iov->iov_num_vfs != 0 || iov->iov_flags & IOV_BUSY) {
190 mtx_unlock(&Giant);
191 return (EBUSY);
192 }
193
194 dinfo->cfg.iov = NULL;
195
196 if (iov->iov_cdev) {
197 destroy_dev(iov->iov_cdev);
198 iov->iov_cdev = NULL;
199 }
200 nvlist_destroy(iov->iov_schema);
201
202 free(iov, M_SRIOV);
203 mtx_unlock(&Giant);
204
205 return (0);
206 }
207
208 static nvlist_t *
pci_iov_build_schema(nvlist_t ** pf,nvlist_t ** vf)209 pci_iov_build_schema(nvlist_t **pf, nvlist_t **vf)
210 {
211 nvlist_t *schema, *pf_driver, *vf_driver;
212
213 /* We always take ownership of the schemas. */
214 pf_driver = *pf;
215 *pf = NULL;
216 vf_driver = *vf;
217 *vf = NULL;
218
219 schema = pci_iov_schema_alloc_node();
220 if (schema == NULL)
221 goto cleanup;
222
223 pci_iov_build_pf_schema(schema, &pf_driver);
224 pci_iov_build_vf_schema(schema, &vf_driver);
225
226 if (nvlist_error(schema) != 0)
227 goto cleanup;
228
229 return (schema);
230
231 cleanup:
232 nvlist_destroy(schema);
233 nvlist_destroy(pf_driver);
234 nvlist_destroy(vf_driver);
235 return (NULL);
236 }
237
238 static void
pci_iov_build_pf_schema(nvlist_t * schema,nvlist_t ** driver_schema)239 pci_iov_build_pf_schema(nvlist_t *schema, nvlist_t **driver_schema)
240 {
241 nvlist_t *pf_schema, *iov_schema;
242
243 pf_schema = pci_iov_schema_alloc_node();
244 if (pf_schema == NULL) {
245 nvlist_set_error(schema, ENOMEM);
246 return;
247 }
248
249 iov_schema = pci_iov_get_pf_subsystem_schema();
250
251 /*
252 * Note that if either *driver_schema or iov_schema is NULL, then
253 * nvlist_move_nvlist will put the schema in the error state and
254 * SR-IOV will fail to initialize later, so we don't have to explicitly
255 * handle that case.
256 */
257 nvlist_move_nvlist(pf_schema, DRIVER_CONFIG_NAME, *driver_schema);
258 nvlist_move_nvlist(pf_schema, IOV_CONFIG_NAME, iov_schema);
259 nvlist_move_nvlist(schema, PF_CONFIG_NAME, pf_schema);
260 *driver_schema = NULL;
261 }
262
263 static void
pci_iov_build_vf_schema(nvlist_t * schema,nvlist_t ** driver_schema)264 pci_iov_build_vf_schema(nvlist_t *schema, nvlist_t **driver_schema)
265 {
266 nvlist_t *vf_schema, *iov_schema;
267
268 vf_schema = pci_iov_schema_alloc_node();
269 if (vf_schema == NULL) {
270 nvlist_set_error(schema, ENOMEM);
271 return;
272 }
273
274 iov_schema = pci_iov_get_vf_subsystem_schema();
275
276 /*
277 * Note that if either *driver_schema or iov_schema is NULL, then
278 * nvlist_move_nvlist will put the schema in the error state and
279 * SR-IOV will fail to initialize later, so we don't have to explicitly
280 * handle that case.
281 */
282 nvlist_move_nvlist(vf_schema, DRIVER_CONFIG_NAME, *driver_schema);
283 nvlist_move_nvlist(vf_schema, IOV_CONFIG_NAME, iov_schema);
284 nvlist_move_nvlist(schema, VF_SCHEMA_NAME, vf_schema);
285 *driver_schema = NULL;
286 }
287
288 static nvlist_t *
pci_iov_get_pf_subsystem_schema(void)289 pci_iov_get_pf_subsystem_schema(void)
290 {
291 nvlist_t *pf;
292
293 pf = pci_iov_schema_alloc_node();
294 if (pf == NULL)
295 return (NULL);
296
297 pci_iov_schema_add_uint16(pf, "num_vfs", IOV_SCHEMA_REQUIRED, -1);
298 pci_iov_schema_add_string(pf, "device", IOV_SCHEMA_REQUIRED, NULL);
299
300 return (pf);
301 }
302
303 static nvlist_t *
pci_iov_get_vf_subsystem_schema(void)304 pci_iov_get_vf_subsystem_schema(void)
305 {
306 nvlist_t *vf;
307
308 vf = pci_iov_schema_alloc_node();
309 if (vf == NULL)
310 return (NULL);
311
312 pci_iov_schema_add_bool(vf, "passthrough", IOV_SCHEMA_HASDEFAULT, 0);
313
314 return (vf);
315 }
316
317 static int
pci_iov_alloc_bar(struct pci_devinfo * dinfo,int bar,pci_addr_t bar_shift)318 pci_iov_alloc_bar(struct pci_devinfo *dinfo, int bar, pci_addr_t bar_shift)
319 {
320 struct resource *res;
321 struct pcicfg_iov *iov;
322 device_t dev, bus;
323 u_long start, end;
324 pci_addr_t bar_size;
325 int rid;
326
327 iov = dinfo->cfg.iov;
328 dev = dinfo->cfg.dev;
329 bus = device_get_parent(dev);
330 rid = iov->iov_pos + PCIR_SRIOV_BAR(bar);
331 bar_size = 1 << bar_shift;
332
333 res = pci_alloc_multi_resource(bus, dev, SYS_RES_MEMORY, &rid, 0ul,
334 ~0ul, 1, iov->iov_num_vfs, RF_ACTIVE);
335
336 if (res == NULL)
337 return (ENXIO);
338
339 iov->iov_bar[bar].res = res;
340 iov->iov_bar[bar].bar_size = bar_size;
341 iov->iov_bar[bar].bar_shift = bar_shift;
342
343 start = rman_get_start(res);
344 end = rman_get_end(res);
345 return (rman_manage_region(&iov->rman, start, end));
346 }
347
348 static void
pci_iov_add_bars(struct pcicfg_iov * iov,struct pci_devinfo * dinfo)349 pci_iov_add_bars(struct pcicfg_iov *iov, struct pci_devinfo *dinfo)
350 {
351 struct pci_iov_bar *bar;
352 uint64_t bar_start;
353 int i;
354
355 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
356 bar = &iov->iov_bar[i];
357 if (bar->res != NULL) {
358 bar_start = rman_get_start(bar->res) +
359 dinfo->cfg.vf.index * bar->bar_size;
360
361 pci_add_bar(dinfo->cfg.dev, PCIR_BAR(i), bar_start,
362 bar->bar_shift);
363 }
364 }
365 }
366
367 static int
pci_iov_parse_config(struct pcicfg_iov * iov,struct pci_iov_arg * arg,nvlist_t ** ret)368 pci_iov_parse_config(struct pcicfg_iov *iov, struct pci_iov_arg *arg,
369 nvlist_t **ret)
370 {
371 void *packed_config;
372 nvlist_t *config;
373 int error;
374
375 config = NULL;
376 packed_config = NULL;
377
378 if (arg->len > pci_iov_max_config) {
379 error = EMSGSIZE;
380 goto out;
381 }
382
383 packed_config = malloc(arg->len, M_SRIOV, M_WAITOK);
384
385 error = copyin(arg->config, packed_config, arg->len);
386 if (error != 0)
387 goto out;
388
389 config = nvlist_unpack(packed_config, arg->len, NV_FLAG_IGNORE_CASE);
390 if (config == NULL) {
391 error = EINVAL;
392 goto out;
393 }
394
395 error = pci_iov_schema_validate_config(iov->iov_schema, config);
396 if (error != 0)
397 goto out;
398
399 error = nvlist_error(config);
400 if (error != 0)
401 goto out;
402
403 *ret = config;
404 config = NULL;
405
406 out:
407 nvlist_destroy(config);
408 free(packed_config, M_SRIOV);
409 return (error);
410 }
411
412 /*
413 * Set the ARI_EN bit in the lowest-numbered PCI function with the SR-IOV
414 * capability. This bit is only writeable on the lowest-numbered PF but
415 * affects all PFs on the device.
416 */
417 static int
pci_iov_set_ari(device_t bus)418 pci_iov_set_ari(device_t bus)
419 {
420 device_t lowest;
421 device_t *devlist;
422 int i, error, devcount, lowest_func, lowest_pos, iov_pos, dev_func;
423 uint16_t iov_ctl;
424
425 /* If ARI is disabled on the downstream port there is nothing to do. */
426 if (!PCIB_ARI_ENABLED(device_get_parent(bus)))
427 return (0);
428
429 error = device_get_children(bus, &devlist, &devcount);
430
431 if (error != 0)
432 return (error);
433
434 lowest = NULL;
435 for (i = 0; i < devcount; i++) {
436 if (pci_find_extcap(devlist[i], PCIZ_SRIOV, &iov_pos) == 0) {
437 dev_func = pci_get_function(devlist[i]);
438 if (lowest == NULL || dev_func < lowest_func) {
439 lowest = devlist[i];
440 lowest_func = dev_func;
441 lowest_pos = iov_pos;
442 }
443 }
444 }
445
446 /*
447 * If we called this function some device must have the SR-IOV
448 * capability.
449 */
450 KASSERT(lowest != NULL,
451 ("Could not find child of %s with SR-IOV capability",
452 device_get_nameunit(bus)));
453
454 iov_ctl = pci_read_config(lowest, iov_pos + PCIR_SRIOV_CTL, 2);
455 iov_ctl |= PCIM_SRIOV_ARI_EN;
456 pci_write_config(lowest, iov_pos + PCIR_SRIOV_CTL, iov_ctl, 2);
457 free(devlist, M_TEMP);
458 return (0);
459 }
460
461 static int
pci_iov_config_page_size(struct pci_devinfo * dinfo)462 pci_iov_config_page_size(struct pci_devinfo *dinfo)
463 {
464 uint32_t page_cap, page_size;
465
466 page_cap = IOV_READ(dinfo, PCIR_SRIOV_PAGE_CAP, 4);
467
468 /*
469 * If the system page size is less than the smallest SR-IOV page size
470 * then round up to the smallest SR-IOV page size.
471 */
472 if (PAGE_SHIFT < PCI_SRIOV_BASE_PAGE_SHIFT)
473 page_size = (1 << 0);
474 else
475 page_size = (1 << (PAGE_SHIFT - PCI_SRIOV_BASE_PAGE_SHIFT));
476
477 /* Check that the device supports the system page size. */
478 if (!(page_size & page_cap))
479 return (ENXIO);
480
481 IOV_WRITE(dinfo, PCIR_SRIOV_PAGE_SIZE, page_size, 4);
482 return (0);
483 }
484
485 static int
pci_iov_init(device_t dev,uint16_t num_vfs,const nvlist_t * config)486 pci_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *config)
487 {
488 const nvlist_t *device, *driver_config;
489
490 device = nvlist_get_nvlist(config, PF_CONFIG_NAME);
491 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME);
492 return (PCI_IOV_INIT(dev, num_vfs, driver_config));
493 }
494
495 static int
pci_iov_init_rman(device_t pf,struct pcicfg_iov * iov)496 pci_iov_init_rman(device_t pf, struct pcicfg_iov *iov)
497 {
498 int error;
499
500 iov->rman.rm_start = 0;
501 iov->rman.rm_end = ~0ul;
502 iov->rman.rm_type = RMAN_ARRAY;
503 snprintf(iov->rman_name, sizeof(iov->rman_name), "%s VF I/O memory",
504 device_get_nameunit(pf));
505 iov->rman.rm_descr = iov->rman_name;
506
507 error = rman_init(&iov->rman);
508 if (error != 0)
509 return (error);
510
511 iov->iov_flags |= IOV_RMAN_INITED;
512 return (0);
513 }
514
515 static int
pci_iov_setup_bars(struct pci_devinfo * dinfo)516 pci_iov_setup_bars(struct pci_devinfo *dinfo)
517 {
518 device_t dev;
519 struct pcicfg_iov *iov;
520 pci_addr_t bar_value, testval;
521 int i, last_64, error;
522
523 iov = dinfo->cfg.iov;
524 dev = dinfo->cfg.dev;
525 last_64 = 0;
526
527 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
528 /*
529 * If a PCI BAR is a 64-bit wide BAR, then it spans two
530 * consecutive registers. Therefore if the last BAR that
531 * we looked at was a 64-bit BAR, we need to skip this
532 * register as it's the second half of the last BAR.
533 */
534 if (!last_64) {
535 pci_read_bar(dev,
536 iov->iov_pos + PCIR_SRIOV_BAR(i),
537 &bar_value, &testval, &last_64);
538
539 if (testval != 0) {
540 error = pci_iov_alloc_bar(dinfo, i,
541 pci_mapsize(testval));
542 if (error != 0)
543 return (error);
544 }
545 } else
546 last_64 = 0;
547 }
548
549 return (0);
550 }
551
552 static void
pci_iov_enumerate_vfs(struct pci_devinfo * dinfo,const nvlist_t * config,uint16_t first_rid,uint16_t rid_stride)553 pci_iov_enumerate_vfs(struct pci_devinfo *dinfo, const nvlist_t *config,
554 uint16_t first_rid, uint16_t rid_stride)
555 {
556 char device_name[VF_MAX_NAME];
557 const nvlist_t *device, *driver_config, *iov_config;
558 device_t bus, dev, vf;
559 struct pcicfg_iov *iov;
560 struct pci_devinfo *vfinfo;
561 size_t size;
562 int i, error;
563 uint16_t vid, did, next_rid;
564
565 iov = dinfo->cfg.iov;
566 dev = dinfo->cfg.dev;
567 bus = device_get_parent(dev);
568 size = dinfo->cfg.devinfo_size;
569 next_rid = first_rid;
570 vid = pci_get_vendor(dev);
571 did = IOV_READ(dinfo, PCIR_SRIOV_VF_DID, 2);
572
573 for (i = 0; i < iov->iov_num_vfs; i++, next_rid += rid_stride) {
574 snprintf(device_name, sizeof(device_name), VF_PREFIX"%d", i);
575 device = nvlist_get_nvlist(config, device_name);
576 iov_config = nvlist_get_nvlist(device, IOV_CONFIG_NAME);
577 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME);
578
579 vf = PCI_CREATE_IOV_CHILD(bus, dev, next_rid, vid, did);
580 if (vf == NULL)
581 break;
582
583 /*
584 * If we are creating passthrough devices then force the ppt
585 * driver to attach to prevent a VF driver from claiming the
586 * VFs.
587 */
588 if (nvlist_get_bool(iov_config, "passthrough"))
589 device_set_devclass_fixed(vf, "ppt");
590
591 vfinfo = device_get_ivars(vf);
592
593 vfinfo->cfg.iov = iov;
594 vfinfo->cfg.vf.index = i;
595
596 pci_iov_add_bars(iov, vfinfo);
597
598 error = PCI_IOV_ADD_VF(dev, i, driver_config);
599 if (error != 0) {
600 device_printf(dev, "Failed to add VF %d\n", i);
601 pci_delete_child(bus, vf);
602 }
603 }
604
605 bus_generic_attach(bus);
606 }
607
608 static int
pci_iov_config(struct cdev * cdev,struct pci_iov_arg * arg)609 pci_iov_config(struct cdev *cdev, struct pci_iov_arg *arg)
610 {
611 device_t bus, dev;
612 struct pci_devinfo *dinfo;
613 struct pcicfg_iov *iov;
614 nvlist_t *config;
615 int i, error;
616 uint16_t rid_off, rid_stride;
617 uint16_t first_rid, last_rid;
618 uint16_t iov_ctl;
619 uint16_t num_vfs, total_vfs;
620 int iov_inited;
621
622 mtx_lock(&Giant);
623 dinfo = cdev->si_drv1;
624 iov = dinfo->cfg.iov;
625 dev = dinfo->cfg.dev;
626 bus = device_get_parent(dev);
627 iov_inited = 0;
628 config = NULL;
629
630 if ((iov->iov_flags & IOV_BUSY) || iov->iov_num_vfs != 0) {
631 mtx_unlock(&Giant);
632 return (EBUSY);
633 }
634 iov->iov_flags |= IOV_BUSY;
635
636 error = pci_iov_parse_config(iov, arg, &config);
637 if (error != 0)
638 goto out;
639
640 num_vfs = pci_iov_config_get_num_vfs(config);
641 total_vfs = IOV_READ(dinfo, PCIR_SRIOV_TOTAL_VFS, 2);
642 if (num_vfs > total_vfs) {
643 error = EINVAL;
644 goto out;
645 }
646
647 error = pci_iov_config_page_size(dinfo);
648 if (error != 0)
649 goto out;
650
651 error = pci_iov_set_ari(bus);
652 if (error != 0)
653 goto out;
654
655 error = pci_iov_init(dev, num_vfs, config);
656 if (error != 0)
657 goto out;
658 iov_inited = 1;
659
660 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, num_vfs, 2);
661
662 rid_off = IOV_READ(dinfo, PCIR_SRIOV_VF_OFF, 2);
663 rid_stride = IOV_READ(dinfo, PCIR_SRIOV_VF_STRIDE, 2);
664
665 first_rid = pci_get_rid(dev) + rid_off;
666 last_rid = first_rid + (num_vfs - 1) * rid_stride;
667
668 /* We don't yet support allocating extra bus numbers for VFs. */
669 if (pci_get_bus(dev) != PCI_RID2BUS(last_rid)) {
670 error = ENOSPC;
671 goto out;
672 }
673
674 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
675 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE);
676 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
677
678 error = pci_iov_init_rman(dev, iov);
679 if (error != 0)
680 goto out;
681
682 iov->iov_num_vfs = num_vfs;
683
684 error = pci_iov_setup_bars(dinfo);
685 if (error != 0)
686 goto out;
687
688 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
689 iov_ctl |= PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE;
690 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
691
692 /* Per specification, we must wait 100ms before accessing VFs. */
693 pause("iov", roundup(hz, 10));
694 pci_iov_enumerate_vfs(dinfo, config, first_rid, rid_stride);
695
696 nvlist_destroy(config);
697 iov->iov_flags &= ~IOV_BUSY;
698 mtx_unlock(&Giant);
699
700 return (0);
701 out:
702 if (iov_inited)
703 PCI_IOV_UNINIT(dev);
704
705 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
706 if (iov->iov_bar[i].res != NULL) {
707 pci_release_resource(bus, dev, SYS_RES_MEMORY,
708 iov->iov_pos + PCIR_SRIOV_BAR(i),
709 iov->iov_bar[i].res);
710 pci_delete_resource(bus, dev, SYS_RES_MEMORY,
711 iov->iov_pos + PCIR_SRIOV_BAR(i));
712 iov->iov_bar[i].res = NULL;
713 }
714 }
715
716 if (iov->iov_flags & IOV_RMAN_INITED) {
717 rman_fini(&iov->rman);
718 iov->iov_flags &= ~IOV_RMAN_INITED;
719 }
720
721 nvlist_destroy(config);
722 iov->iov_num_vfs = 0;
723 iov->iov_flags &= ~IOV_BUSY;
724 mtx_unlock(&Giant);
725 return (error);
726 }
727
728 /* Return true if child is a VF of the given PF. */
729 static int
pci_iov_is_child_vf(struct pcicfg_iov * pf,device_t child)730 pci_iov_is_child_vf(struct pcicfg_iov *pf, device_t child)
731 {
732 struct pci_devinfo *vfinfo;
733
734 vfinfo = device_get_ivars(child);
735
736 if (!(vfinfo->cfg.flags & PCICFG_VF))
737 return (0);
738
739 return (pf == vfinfo->cfg.iov);
740 }
741
742 static int
pci_iov_delete(struct cdev * cdev)743 pci_iov_delete(struct cdev *cdev)
744 {
745 device_t bus, dev, vf, *devlist;
746 struct pci_devinfo *dinfo;
747 struct pcicfg_iov *iov;
748 int i, error, devcount;
749 uint32_t iov_ctl;
750
751 mtx_lock(&Giant);
752 dinfo = cdev->si_drv1;
753 iov = dinfo->cfg.iov;
754 dev = dinfo->cfg.dev;
755 bus = device_get_parent(dev);
756 devlist = NULL;
757
758 if (iov->iov_flags & IOV_BUSY) {
759 mtx_unlock(&Giant);
760 return (EBUSY);
761 }
762
763 if (iov->iov_num_vfs == 0) {
764 mtx_unlock(&Giant);
765 return (ECHILD);
766 }
767
768 iov->iov_flags |= IOV_BUSY;
769
770 error = device_get_children(bus, &devlist, &devcount);
771
772 if (error != 0)
773 goto out;
774
775 for (i = 0; i < devcount; i++) {
776 vf = devlist[i];
777
778 if (!pci_iov_is_child_vf(iov, vf))
779 continue;
780
781 error = device_detach(vf);
782 if (error != 0) {
783 device_printf(dev,
784 "Could not disable SR-IOV: failed to detach VF %s\n",
785 device_get_nameunit(vf));
786 goto out;
787 }
788 }
789
790 for (i = 0; i < devcount; i++) {
791 vf = devlist[i];
792
793 if (pci_iov_is_child_vf(iov, vf))
794 pci_delete_child(bus, vf);
795 }
796 PCI_IOV_UNINIT(dev);
797
798 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
799 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE);
800 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
801 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, 0, 2);
802
803 iov->iov_num_vfs = 0;
804
805 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
806 if (iov->iov_bar[i].res != NULL) {
807 pci_release_resource(bus, dev, SYS_RES_MEMORY,
808 iov->iov_pos + PCIR_SRIOV_BAR(i),
809 iov->iov_bar[i].res);
810 pci_delete_resource(bus, dev, SYS_RES_MEMORY,
811 iov->iov_pos + PCIR_SRIOV_BAR(i));
812 iov->iov_bar[i].res = NULL;
813 }
814 }
815
816 if (iov->iov_flags & IOV_RMAN_INITED) {
817 rman_fini(&iov->rman);
818 iov->iov_flags &= ~IOV_RMAN_INITED;
819 }
820
821 error = 0;
822 out:
823 free(devlist, M_TEMP);
824 iov->iov_flags &= ~IOV_BUSY;
825 mtx_unlock(&Giant);
826 return (error);
827 }
828
829 static int
pci_iov_get_schema_ioctl(struct cdev * cdev,struct pci_iov_schema * output)830 pci_iov_get_schema_ioctl(struct cdev *cdev, struct pci_iov_schema *output)
831 {
832 struct pci_devinfo *dinfo;
833 void *packed;
834 size_t output_len, size;
835 int error;
836
837 packed = NULL;
838
839 mtx_lock(&Giant);
840 dinfo = cdev->si_drv1;
841 packed = nvlist_pack(dinfo->cfg.iov->iov_schema, &size);
842 mtx_unlock(&Giant);
843
844 if (packed == NULL) {
845 error = ENOMEM;
846 goto fail;
847 }
848
849 output_len = output->len;
850 output->len = size;
851 if (size <= output_len) {
852 error = copyout(packed, output->schema, size);
853
854 if (error != 0)
855 goto fail;
856
857 output->error = 0;
858 } else
859 /*
860 * If we return an error then the ioctl code won't copyout
861 * output back to userland, so we flag the error in the struct
862 * instead.
863 */
864 output->error = EMSGSIZE;
865
866 error = 0;
867
868 fail:
869 free(packed, M_NVLIST);
870
871 return (error);
872 }
873
874 static int
pci_iov_ioctl(struct cdev * dev,u_long cmd,caddr_t data,int fflag,struct thread * td)875 pci_iov_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
876 struct thread *td)
877 {
878
879 switch (cmd) {
880 case IOV_CONFIG:
881 return (pci_iov_config(dev, (struct pci_iov_arg *)data));
882 case IOV_DELETE:
883 return (pci_iov_delete(dev));
884 case IOV_GET_SCHEMA:
885 return (pci_iov_get_schema_ioctl(dev,
886 (struct pci_iov_schema *)data));
887 default:
888 return (EINVAL);
889 }
890 }
891
892 struct resource *
pci_vf_alloc_mem_resource(device_t dev,device_t child,int * rid,u_long start,u_long end,u_long count,u_int flags)893 pci_vf_alloc_mem_resource(device_t dev, device_t child, int *rid, u_long start,
894 u_long end, u_long count, u_int flags)
895 {
896 struct pci_devinfo *dinfo;
897 struct pcicfg_iov *iov;
898 struct pci_map *map;
899 struct resource *res;
900 struct resource_list_entry *rle;
901 u_long bar_start, bar_end;
902 pci_addr_t bar_length;
903 int error;
904
905 dinfo = device_get_ivars(child);
906 iov = dinfo->cfg.iov;
907
908 map = pci_find_bar(child, *rid);
909 if (map == NULL)
910 return (NULL);
911
912 bar_length = 1 << map->pm_size;
913 bar_start = map->pm_value;
914 bar_end = bar_start + bar_length - 1;
915
916 /* Make sure that the resource fits the constraints. */
917 if (bar_start >= end || bar_end <= bar_start || count != 1)
918 return (NULL);
919
920 /* Clamp the resource to the constraints if necessary. */
921 if (bar_start < start)
922 bar_start = start;
923 if (bar_end > end)
924 bar_end = end;
925 bar_length = bar_end - bar_start + 1;
926
927 res = rman_reserve_resource(&iov->rman, bar_start, bar_end,
928 bar_length, flags, child);
929 if (res == NULL)
930 return (NULL);
931
932 rle = resource_list_add(&dinfo->resources, SYS_RES_MEMORY, *rid,
933 bar_start, bar_end, 1);
934 if (rle == NULL) {
935 rman_release_resource(res);
936 return (NULL);
937 }
938
939 rman_set_rid(res, *rid);
940
941 if (flags & RF_ACTIVE) {
942 error = bus_activate_resource(child, SYS_RES_MEMORY, *rid, res);
943 if (error != 0) {
944 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY,
945 *rid);
946 rman_release_resource(res);
947 return (NULL);
948 }
949 }
950 rle->res = res;
951
952 return (res);
953 }
954
955 int
pci_vf_release_mem_resource(device_t dev,device_t child,int rid,struct resource * r)956 pci_vf_release_mem_resource(device_t dev, device_t child, int rid,
957 struct resource *r)
958 {
959 struct pci_devinfo *dinfo;
960 struct resource_list_entry *rle;
961 int error;
962
963 dinfo = device_get_ivars(child);
964
965 if (rman_get_flags(r) & RF_ACTIVE) {
966 error = bus_deactivate_resource(child, SYS_RES_MEMORY, rid, r);
967 if (error != 0)
968 return (error);
969 }
970
971 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, rid);
972 if (rle != NULL) {
973 rle->res = NULL;
974 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY,
975 rid);
976 }
977
978 return (rman_release_resource(r));
979 }
980
981