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Searched refs:wrmsr (Results 1 – 25 of 50) sorted by relevance

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/trueos/sys/i386/i386/
HDinitcpu.c136 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */ in init_bluelightning()
138 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */ in init_bluelightning()
141 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff); in init_bluelightning()
143 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */ in init_bluelightning()
145 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */ in init_bluelightning()
467 wrmsr(0x0107, fcr); in init_winchip()
551 wrmsr(MSR_APICBASE, apicbase); in init_ppro()
568 wrmsr(MSR_APICBASE, apicbase); in ppro_reenable_apic()
604 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3); in init_mendocino()
646 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); in init_via()
[all …]
HDperfmon.c141 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0); in perfmon_setup()
185 wrmsr(msr_pmc[pmc], pmc_shadow[pmc]); in perfmon_start()
236 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0); in perfmon_reset()
254 wrmsr(msr_ctl[pmc], 0); in writectl6()
256 wrmsr(msr_ctl[pmc], ctl_shadow[pmc]); in writectl6()
290 wrmsr(msr_ctl[0], newval); in writectl5()
HDi686_mem.c323 wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE); in i686_mrstoreone()
336 wrmsr(msr, msrv); in i686_mrstoreone()
348 wrmsr(msr, msrv); in i686_mrstoreone()
360 wrmsr(msr, msrv); in i686_mrstoreone()
376 wrmsr(msr, msrv); in i686_mrstoreone()
385 wrmsr(msr + 1, msrv); in i686_mrstoreone()
393 wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE); in i686_mrstoreone()
674 wrmsr(MSR_MTRRdefType, mtrrdef); in i686_mrAPinit()
HDlongrun.c146 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr); in tmx86_set_longrun_mode()
151 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr); in tmx86_set_longrun_mode()
HDk6_mem.c169 wrmsr(UWCCR, reg); in k6_mrset()
/trueos/sys/amd64/vmm/intel/
HDvmx_msr.c325 wrmsr(MSR_LSTAR, guest_msrs[IDX_MSR_LSTAR]); in vmx_msr_guest_enter()
326 wrmsr(MSR_CSTAR, guest_msrs[IDX_MSR_CSTAR]); in vmx_msr_guest_enter()
327 wrmsr(MSR_STAR, guest_msrs[IDX_MSR_STAR]); in vmx_msr_guest_enter()
328 wrmsr(MSR_SF_MASK, guest_msrs[IDX_MSR_SF_MASK]); in vmx_msr_guest_enter()
329 wrmsr(MSR_KGSBASE, guest_msrs[IDX_MSR_KGSBASE]); in vmx_msr_guest_enter()
345 wrmsr(MSR_LSTAR, host_msrs[IDX_MSR_LSTAR]); in vmx_msr_guest_exit()
346 wrmsr(MSR_CSTAR, host_msrs[IDX_MSR_CSTAR]); in vmx_msr_guest_exit()
347 wrmsr(MSR_STAR, host_msrs[IDX_MSR_STAR]); in vmx_msr_guest_exit()
348 wrmsr(MSR_SF_MASK, host_msrs[IDX_MSR_SF_MASK]); in vmx_msr_guest_exit()
/trueos/sys/dev/hyperv/vmbus/
HDhv_hv.c228 wrmsr(HV_X64_MSR_GUEST_OS_ID, os_guest_info); in hv_vmbus_init()
244 wrmsr(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64_t); in hv_vmbus_init()
265 wrmsr(HV_X64_MSR_HYPERCALL, in hv_vmbus_init()
285 wrmsr(HV_X64_MSR_HYPERCALL, in hv_vmbus_cleanup()
395 wrmsr(HV_X64_MSR_SIMP, simp.as_uint64_t); in hv_vmbus_synic_init()
405 wrmsr(HV_X64_MSR_SIEFP, siefp.as_uint64_t); in hv_vmbus_synic_init()
413 wrmsr(HV_X64_MSR_SINT0 + HV_VMBUS_MESSAGE_SINT, in hv_vmbus_synic_init()
420 wrmsr(HV_X64_MSR_SCONTROL, sctrl.as_uint64_t); in hv_vmbus_synic_init()
454 wrmsr( in hv_vmbus_synic_cleanup()
462 wrmsr(HV_X64_MSR_SIMP, simp.as_uint64_t); in hv_vmbus_synic_cleanup()
[all …]
/trueos/sys/amd64/vmm/amd/
HDsvm_msr.c93 wrmsr(MSR_LSTAR, host_msrs[IDX_MSR_LSTAR]); in svm_msr_guest_exit()
94 wrmsr(MSR_CSTAR, host_msrs[IDX_MSR_CSTAR]); in svm_msr_guest_exit()
95 wrmsr(MSR_STAR, host_msrs[IDX_MSR_STAR]); in svm_msr_guest_exit()
96 wrmsr(MSR_SF_MASK, host_msrs[IDX_MSR_SF_MASK]); in svm_msr_guest_exit()
/trueos/sys/amd64/amd64/
HDinitcpu.c110 wrmsr(0xc0011029, rdmsr(0xc0011029) | 1); in init_amd()
138 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); in init_via()
151 wrmsr(0x1107, rdmsr(0x1107) | (1 << 28)); in init_via()
182 wrmsr(MSR_EFER, msr); in initializecpu()
HDamd64_mem.c329 wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE); in amd64_mrstoreone()
342 wrmsr(msr, msrv); in amd64_mrstoreone()
354 wrmsr(msr, msrv); in amd64_mrstoreone()
366 wrmsr(msr, msrv); in amd64_mrstoreone()
382 wrmsr(msr, msrv); in amd64_mrstoreone()
391 wrmsr(msr + 1, msrv); in amd64_mrstoreone()
399 wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE); in amd64_mrstoreone()
708 wrmsr(MSR_MTRRdefType, mtrrdef); in amd64_mrAPinit()
HDcpu_switch.S434 wrmsr
438 wrmsr
442 wrmsr
447 wrmsr
453 wrmsr
457 wrmsr
461 wrmsr
464 wrmsr
HDmp_machdep.c682 wrmsr(MSR_FSBASE, 0); /* User value */ in init_secondary()
683 wrmsr(MSR_GSBASE, (u_int64_t)pc); in init_secondary()
684 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */ in init_secondary()
702 wrmsr(MSR_EFER, msr); in init_secondary()
703 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); in init_secondary()
704 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); in init_secondary()
707 wrmsr(MSR_STAR, msr); in init_secondary()
708 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); in init_secondary()
HDexception.S501 wrmsr
587 wrmsr
723 wrmsr
744 wrmsr
761 wrmsr /* May trap if non-canonical, but only for TLS. */
HDmachdep.c619 wrmsr(MSR_MPERF, 0); in cpu_est_clockrate()
620 wrmsr(MSR_APERF, 0); in cpu_est_clockrate()
824 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); in cpu_idle()
1859 wrmsr(MSR_FSBASE, 0); /* User value */ in hammer_time()
1860 wrmsr(MSR_GSBASE, (u_int64_t)pc); in hammer_time()
1861 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ in hammer_time()
1990 wrmsr(MSR_EFER, msr); in hammer_time()
1991 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); in hammer_time()
1992 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); in hammer_time()
1995 wrmsr(MSR_STAR, msr); in hammer_time()
[all …]
HDmpboot.S106 wrmsr
/trueos/sys/x86/x86/
HDmca.c443 wrmsr(MSR_MC_STATUS(bank), 0); in mca_check_status()
544 wrmsr(MSR_MC_CTL2(bank), limit); in cmci_update()
577 wrmsr(MSR_MC_CTL2(bank), limit); in cmci_update()
805 wrmsr(MSR_MC_CTL2(i), ctl); in cmci_monitor()
816 wrmsr(MSR_MC_CTL2(i), ctl); in cmci_monitor()
823 wrmsr(MSR_MC_CTL2(i), ctl); in cmci_monitor()
850 wrmsr(MSR_MC_CTL2(i), ctl); in cmci_resume()
876 wrmsr(MSR_MCG_CTL, MCG_CTL_ENABLE); in _mca_init()
891 wrmsr(MSR_MC0_CTL_MASK, mask | (1UL << 5)); in _mca_init()
913 wrmsr(MSR_MC_CTL(i), ctl); in _mca_init()
[all …]
/trueos/sys/dev/hwpmc/
HDhwpmc_uncore.c156 wrmsr(SELECTSEL(uncore_cputype) + n, 0); in uncore_pcpu_fini()
158 wrmsr(UCF_CTRL, 0); in uncore_pcpu_fini()
338 wrmsr(UCF_CTRL, ucfc->pc_ucfctrl); in ucf_start_pmc()
343 wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl); in ucf_start_pmc()
373 wrmsr(UCF_CTRL, ucfc->pc_ucfctrl); in ucf_stop_pmc()
378 wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl); in ucf_stop_pmc()
408 wrmsr(UCF_CTRL, 0); /* Turn off fixed counters */ in ucf_write_pmc()
409 wrmsr(UCF_CTR0 + ri, v); in ucf_write_pmc()
410 wrmsr(UCF_CTRL, cc->pc_ucfctrl); in ucf_write_pmc()
1060 wrmsr(MSR_GQ_SNOOP_MESF,0x2); in ucp_start_pmc()
[all …]
HDhwpmc_piv.c662 wrmsr(P4_CCCR_MSR_FIRST + i, in p4_pcpu_fini()
772 wrmsr(pd->pm_pmc_msr, v); in p4_write_pmc()
1198 wrmsr(escrmsr, escrvalue | escrtbits); in p4_start_pmc()
1199 wrmsr(pd->pm_cccr_msr, cccrvalue | cccrtbits | P4_CCCR_ENABLE); in p4_start_pmc()
1227 wrmsr(pd->pm_pmc_msr, in p4_start_pmc()
1239 wrmsr(pd->pm_cccr_msr, cccrvalue & ~P4_CCCR_ENABLE); in p4_start_pmc()
1278 wrmsr(escrmsr, escrvalue); in p4_start_pmc()
1279 wrmsr(pd->pm_cccr_msr, cccrvalue); in p4_start_pmc()
1324 wrmsr(pd->pm_cccr_msr, in p4_stop_pmc()
1362 wrmsr(pd->pm_cccr_msr, cccrvalue & ~P4_CCCR_ENABLE); in p4_stop_pmc()
[all …]
HDhwpmc_amd.c345 wrmsr(pd->pm_perfctr, v); in amd_write_pmc()
581 wrmsr(pd->pm_evsel, config); in amd_start_pmc()
617 wrmsr(pd->pm_evsel, config); in amd_stop_pmc()
686 wrmsr(evsel, config & ~AMD_PMC_ENABLE); in amd_intr()
687 wrmsr(perfctr, AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v)); in amd_intr()
693 wrmsr(evsel, config | AMD_PMC_ENABLE); in amd_intr()
827 wrmsr(AMD_PMC_EVSEL_0 + i, evsel); in amd_pcpu_fini()
HDhwpmc_ppro.c320 wrmsr(P6_MSR_EVSEL0, _config | _enable); \
444 wrmsr(pd->pm_pmc_msr, v & P6_PERFCTR_WRITE_MASK); in p6_write_pmc()
634 wrmsr(pd->pm_evsel_msr, config); in p6_start_pmc()
663 wrmsr(pd->pm_evsel_msr, 0); /* stop hw */ in p6_stop_pmc()
690 wrmsr(P6_MSR_EVSEL0, perf0cfg & ~P6_EVSEL_EN); in p6_intr()
714 wrmsr(P6_MSR_PERFCTR0 + ri, in p6_intr()
HDhwpmc_core.c182 wrmsr(IAP_EVSEL0 + n, msr); in core_pcpu_fini()
187 wrmsr(IAF_CTRL, msr); in core_pcpu_fini()
411 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); in iaf_start_pmc()
417 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & in iaf_start_pmc()
454 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); in iaf_stop_pmc()
460 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & in iaf_stop_pmc()
494 wrmsr(IAF_CTRL, msr); in iaf_write_pmc()
496 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); in iaf_write_pmc()
500 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); in iaf_write_pmc()
2409 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); in iap_start_pmc()
[all …]
/trueos/sys/dev/agp/
HDagp_nvidia.c414 wrmsr(IORR_BASE0 + 2 * iorr_addr, base); in nvidia_init_iorr()
415 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask); in nvidia_init_iorr()
419 wrmsr(SYSCFG, sys); in nvidia_init_iorr()
/trueos/sys/x86/cpufreq/
HDpowernow.c149 wrmsr(MSR_AMDK7_FIDVID_CTL, \
300 wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_FIDC); in pn7_setfidvid()
302 wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_VIDC); in pn7_setfidvid()
304 wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_VIDC); in pn7_setfidvid()
306 wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_FIDC); in pn7_setfidvid()
/trueos/sys/boot/i386/libi386/
HDamd64_tramp.S83 wrmsr
/trueos/sys/amd64/acpica/
HDacpi_wakecode.S164 wrmsr

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