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Searched refs:v8i8 (Results 1 – 18 of 18) sorted by relevance

/trueos/contrib/llvm/lib/Target/ARM/
HDARMCallingConv.td27 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
46 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
60 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
72 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
88 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
138 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
148 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
166 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
178 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
HDARMTargetTransformInfo.cpp224 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
225 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
226 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
227 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
235 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
497 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost}, in getArithmeticInstrCost()
498 { ISD::UDIV, MVT::v8i8, ReciprocalDivCost}, in getArithmeticInstrCost()
499 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
500 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
HDARMInstrNEON.td1020 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
1309 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
1966 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
2009 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
3133 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
3136 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
3181 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3182 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3204 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3206 v8i8, v8i16, OpNode>;
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HDARMRegisterInfo.td284 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
293 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
298 def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
HDARMISelDAGToDAG.cpp1799 case MVT::v8i8: OpcodeIndex = 0; break; in SelectVLD()
1935 case MVT::v8i8: OpcodeIndex = 0; break; in SelectVST()
2097 case MVT::v8i8: OpcodeIndex = 0; break; in SelectVLDSTLane()
2209 case MVT::v8i8: OpcodeIndex = 0; break; in SelectVLDDup()
2756 case MVT::v8i8: Opc = ARM::VZIPd8; break; in Select()
2776 case MVT::v8i8: Opc = ARM::VUZPd8; break; in Select()
2796 case MVT::v8i8: Opc = ARM::VTRNd8; break; in Select()
HDARMISelLowering.cpp461 addDRTypeForNEON(MVT::v8i8); in ARMTargetLowering()
553 setOperationAction(ISD::SDIV, MVT::v8i8, Custom); in ARMTargetLowering()
555 setOperationAction(ISD::UDIV, MVT::v8i8, Custom); in ARMTargetLowering()
603 MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8, in ARMTargetLowering()
981 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16: in findRepresentativeClass()
3753 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes); in LowerFCOPYSIGN()
4005 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in getCTPOP16BitCounts()
4033 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8, in lowerCTPOP16BitElements()
4324 VT = is128Bits ? MVT::v16i8 : MVT::v8i8; in isNEONModifiedImm()
4616 return VT == MVT::v8i8 && M.size() == 8; in isVTBLMask()
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/trueos/contrib/llvm/lib/Target/AArch64/
HDAArch64InstrNEON.td87 [(set (v8i8 VPR64:$Rd),
88 (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
142 [(set (v8i8 VPR64:$Rd),
143 (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
253 def MLAvvv_8B: NeonI_3VSame_Constraint_impl<"mla", ".8b", VPR64, v8i8,
266 def MLSvvv_8B: NeonI_3VSame_Constraint_impl<"mls", ".8b", VPR64, v8i8,
356 (xor node:$in, (bitconvert (v8i8 Neon_AllOne)))>;
409 def BSLvvv_8B : NeonI_3VSame_Constraint_impl<"bsl", ".8b", VPR64, v8i8,
433 def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
459 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
[all …]
HDAArch64RegisterInfo.td163 [f64, v2f32, v2i32, v4i16, v8i8, v1i64, v1f64],
171 [f64, v2f32, v2i32, v4i16, v8i8, v1i64, v1f64],
HDAArch64CallingConv.td64 CCIfType<[v8i8, v4i16, v2i32, v2f32, v1i64, v1f64], CCBitConvertToType<f64>>,
HDAArch64ISelLowering.cpp65 addRegisterClass(MVT::v8i8, &AArch64::FPR64RegClass); in AArch64TargetLowering()
285 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); in AArch64TargetLowering()
301 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); in AArch64TargetLowering()
324 setOperationAction(ISD::SETCC, MVT::v8i8, Custom); in AArch64TargetLowering()
2916 VT = is128Bits ? MVT::v16i8 : MVT::v8i8; in isNeonModifiedImm()
3415 EVT CanonicalVT = VT.is128BitVector() ? MVT::v16i8 : MVT::v8i8; in PerformORCombine()
/trueos/contrib/llvm/include/llvm/CodeGen/
HDValueTypes.h73 v8i8 = 22, // 8 x i8 enumerator
209 return (SimpleTy == MVT::v8i8 || SimpleTy == MVT::v4i16 || in is64BitVector()
276 case v8i8 : in getVectorElementType()
327 case v8i8 : in getVectorNumElements()
397 case v8i8: in getSizeInBits()
516 if (NumElements == 8) return MVT::v8i8; in getVectorVT()
HDValueTypes.td45 def v8i8 : ValueType<64 , 22>; // 8 x i8 vector value
/trueos/contrib/llvm/lib/IR/
HDValueTypes.cpp140 case MVT::v8i8: return "v8i8"; in getEVTString()
208 case MVT::v8i8: return VectorType::get(Type::getInt8Ty(Context), 8); in getTypeForEVT()
/trueos/contrib/llvm/include/llvm/IR/
HDIntrinsicsARM.td158 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
159 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
160 // Overall, the classes range from 2 to 6 v8i8 arguments.
HDIntrinsics.td146 def llvm_v8i8_ty : LLVMType<v8i8>; // 8 x i8
/trueos/contrib/llvm/lib/Target/X86/
HDX86TargetTransformInfo.cpp415 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, in getCastInstrCost()
428 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, in getCastInstrCost()
440 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 }, in getCastInstrCost()
HDX86ISelLowering.cpp883 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); in resetOperationActions()
887 setOperationAction(ISD::AND, MVT::v8i8, Expand); in resetOperationActions()
891 setOperationAction(ISD::OR, MVT::v8i8, Expand); in resetOperationActions()
895 setOperationAction(ISD::XOR, MVT::v8i8, Expand); in resetOperationActions()
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); in resetOperationActions()
904 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); in resetOperationActions()
908 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); in resetOperationActions()
1161 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom); in resetOperationActions()
8692 SVT == MVT::v8i8 || SVT == MVT::v8i16) && in lowerUINT_TO_FP_vec()
18989 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) { in PerformSINT_TO_FPCombine()
/trueos/contrib/llvm/utils/TableGen/
HDCodeGenTarget.cpp81 case MVT::v8i8: return "MVT::v8i8"; in getEnumName()