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Searched refs:upper_32_bits (Results 1 – 25 of 26) sorted by relevance

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/trueos/sys/dev/drm2/radeon/
HDevergreen_cs.c2040 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2086 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2113 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2141 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2253 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2311 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2349 ib[idx+3] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2391 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2413 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2435 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
[all …]
HDr600_cs.c1810 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); in r600_packet3_check()
1851 ib[idx+1] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1903 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1944 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in r600_packet3_check()
1974 ib[idx+3] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2012 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2034 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in r600_packet3_check()
2141 (upper_32_bits(offset64) & 0xff); in r600_packet3_check()
2283 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2302 ib[idx+4] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
[all …]
HDradeon_cursor.c135 upper_32_bits(gpu_addr)); in radeon_set_cursor()
141 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr)); in radeon_set_cursor()
143 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr)); in radeon_set_cursor()
HDni.c940 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in cayman_fence_ring_emit()
967 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in cayman_ring_ib_execute()
1165 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF); in cayman_cp_resume()
1236 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in cayman_dma_ring_ib_execute()
1247 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in cayman_dma_ring_ib_execute()
1328 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF); in cayman_dma_resume()
1943 radeon_ring_write(ring, upper_32_bits(pe) & 0xff); in cayman_vm_set_page()
1956 radeon_ring_write(ring, upper_32_bits(value)); in cayman_vm_set_page()
1968 radeon_ring_write(ring, upper_32_bits(pe) & 0xff); in cayman_vm_set_page()
1981 radeon_ring_write(ring, upper_32_bits(value)); in cayman_vm_set_page()
HDrv770.c61 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
62 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
64 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
65 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
949 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in rv770_copy_dma()
950 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in rv770_copy_dma()
HDsi.c1818 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in si_fence_ring_emit()
1850 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); in si_ring_ib_execute()
1863 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in si_ring_ib_execute()
2070 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in si_cp_resume()
2103 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); in si_cp_resume()
2129 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3003 radeon_ring_write(ring, upper_32_bits(pe)); in si_vm_set_page()
3016 radeon_ring_write(ring, upper_32_bits(value)); in si_vm_set_page()
3030 radeon_ring_write(ring, upper_32_bits(pe) & 0xff); in si_vm_set_page()
3043 radeon_ring_write(ring, upper_32_bits(value)); in si_vm_set_page()
[all …]
HDrv515.c384 upper_32_bits(rdev->mc.vram_start)); in rv515_mc_resume()
386 upper_32_bits(rdev->mc.vram_start)); in rv515_mc_resume()
389 upper_32_bits(rdev->mc.vram_start)); in rv515_mc_resume()
391 upper_32_bits(rdev->mc.vram_start)); in rv515_mc_resume()
487 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); in rv515_mc_program()
HDrs400.c165 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; in rs400_gart_enable()
224 ((upper_32_bits(addr) & 0xff) << 4) | in rs400_gart_set_page()
HDr600.c2264 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in r600_cp_resume()
2391 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); in r600_dma_resume()
2535 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff); in r600_dma_ring_test()
2579 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in r600_fence_ring_emit()
2620 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); in r600_semaphore_ring_emit()
2646 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in r600_dma_fence_ring_emit()
2673 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in r600_dma_semaphore_ring_emit()
2751 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | in r600_copy_dma()
2752 (upper_32_bits(src_offset) & 0xff))); in r600_copy_dma()
3071 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); in r600_ring_ib_execute()
[all …]
HDevergreen.c229 upper_32_bits(crtc_base)); in evergreen_page_flip()
234 upper_32_bits(crtc_base)); in evergreen_page_flip()
1448 upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
1450 upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
1456 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
1622 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); in evergreen_ring_ib_execute()
1633 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in evergreen_ring_ib_execute()
1777 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in evergreen_cp_resume()
3396 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in evergreen_dma_fence_ring_emit()
3426 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in evergreen_dma_ring_ib_execute()
[all …]
HDr520.c162 S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); in r520_mc_program()
HDatombios_crtc.c1210 upper_32_bits(fb_location)); in dce4_crtc_do_set_base()
1212 upper_32_bits(fb_location)); in dce4_crtc_do_set_base()
1374 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); in avivo_crtc_do_set_base()
1375 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); in avivo_crtc_do_set_base()
1377 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); in avivo_crtc_do_set_base()
1378 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); in avivo_crtc_do_set_base()
HDevergreen_blit_kms.c144 sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) | in set_vtx_resource()
606 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF); in set_default_state()
HDr600_blit_kms.c166 sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) | in set_vtx_resource()
447 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF); in set_default_state()
HDr300.c85 ((upper_32_bits(addr) & 0xff) << 24) | in rv370_pcie_gart_set_page()
1323 upper_32_bits(rdev->mc.agp_base) & 0xff); in r300_mc_program()
HDradeon_cp.c237 u32 agp_base_hi = upper_32_bits(agp_base); in radeon_write_agp_base()
937 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; in radeon_set_igpgart()
HDr600_cp.c1868 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, upper_32_bits(rptr_addr)); in r600_cp_init_ring_buffer()
2424 OUT_RING((upper_32_bits(offset) & 0xff)); in r600_cp_dispatch_indirect()
/trueos/sys/dev/drm/
HDati_pcigart.c199 (upper_32_bits(entry_addr) & 0xff) << 4; in drm_ati_pcigart_init()
206 (upper_32_bits(entry_addr) & 0xff) << 24; in drm_ati_pcigart_init()
HDradeon_cs.c407 ib_chunk->kdata[offset_dw + 2] += (upper_32_bits(offset) & 0xff); in r600_cs_packet3()
437 ib_chunk->kdata[offset_dw + 3] += (upper_32_bits(offset) & 0xff); in r600_cs_packet3()
472 ib_chunk->kdata[offset_dw + 3] += (upper_32_bits(offset) & 0xff); in r600_cs_packet3()
491 ib_chunk->kdata[offset_dw + 3] += (upper_32_bits(offset) & 0xff); in r600_cs_packet3()
631 ib_chunk->kdata[offset_dw + (i * 7) + 2 + 2] += (upper_32_bits(offset) & 0xff); in r600_cs_packet3()
HDradeon_cp.c230 u32 agp_base_hi = upper_32_bits(agp_base); in radeon_write_agp_base()
878 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; in radeon_set_igpgart()
HDdrmP.h553 #define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) macro
HDr600_cp.c1679 upper_32_bits(rptr_addr)); in r600_cp_init_ring_buffer()
2229 OUT_RING((upper_32_bits(offset) & 0xff)); in r600_cp_dispatch_indirect()
/trueos/sys/dev/oce/
HDoce_mbox.c1210 sgl->pa_hi = htole32(upper_32_bits(pdma_mem->paddr)); in oce_update_multicast()
1248 sgl->pa_hi = htole32(upper_32_bits(dma_mem->paddr)); in oce_pass_through_mbox()
1496 sgl->pa_hi = upper_32_bits(pdma_mem->paddr); in oce_mbox_write_flashrom()
1646 fwcmd->params.req.address_upper = upper_32_bits(pdma_mem->paddr); in oce_mbox_lancer_write_flashrom()
1944 sgl->pa_hi = htole32(upper_32_bits(dma.paddr)); in oce_mbox_read_transrecv_data()
2070 sgl->pa_hi = htole32(upper_32_bits(dma.paddr)); in oce_get_profile_config()
2172 sgl->pa_hi = htole32(upper_32_bits(dma.paddr)); in oce_get_func_config()
HDoce_if.h198 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) macro
/trueos/sys/dev/drm2/
HDdrmP.h1699 #define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) macro

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