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Searched refs:setRegClass (Results 1 – 8 of 8) sorted by relevance

/trueos/contrib/llvm/lib/CodeGen/
HDMachineRegisterInfo.cpp46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() function in MachineRegisterInfo
64 setRegClass(Reg, NewRC); in constrainRegClass()
96 setRegClass(Reg, NewRC); in recomputeRegClass()
HDRegisterCoalescer.cpp839 MRI->setRegClass(DstReg, CP.getNewRC()); in reMaterializeTrivialDef()
1132 MRI->setRegClass(CP.getDstReg(), CP.getNewRC()); in joinCopy()
HDMachineLICM.cpp1363 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]); in EliminateCSE()
/trueos/contrib/llvm/lib/Target/PowerPC/
HDPPCFastISel.cpp390 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); in PPCComputeAddress()
1131 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1135 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
1148 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1157 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
2189 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); in FastEmitInst_ri()
2191 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass); in FastEmitInst_ri()
/trueos/contrib/llvm/lib/Target/R600/
HDAMDGPUInstrInfo.cpp346 MRI.setRegClass(MO.getReg(), newRegClass); in convertToISA()
HDSIISelLowering.cpp1353 MRI.setRegClass(VReg, RC); in AdjustInstrPostInstrSelection()
/trueos/contrib/llvm/include/llvm/CodeGen/
HDMachineRegisterInfo.h348 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
/trueos/contrib/llvm/lib/CodeGen/SelectionDAG/
HDInstrEmitter.cpp629 MRI->setRegClass(NewVReg, SRC); in EmitRegSequence()