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Searched refs:rs1 (Results 1 – 25 of 42) sorted by relevance

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/trueos/contrib/llvm/patches/
HDpatch-r262261-llvm-r198740-sparc.diff55 "mulx $rs1, $rs2, $rd",
56 [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
58 - (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
59 - "mulx $rs1, $i, $rd",
60 - [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$i)))]>;
61 + (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
62 + "mulx $rs1, $simm13, $rd",
63 + [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>;
68 "sdivx $rs1, $rs2, $rd",
69 [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>;
[all …]
HDpatch-r262261-llvm-r199033-sparc.diff164 + (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
165 + "fadds $rs1, $rs2, $rd",
166 + [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))]>;
171 + (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
172 + "faddd $rs1, $rs2, $rd",
173 + [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))]>;
178 + (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
179 + "faddq $rs1, $rs2, $rd",
180 + [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
187 + (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
[all …]
HDpatch-r262261-llvm-r198591-sparc.diff89 + (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
90 + !strconcat(OpcStr, " $rs1, $rs2, $rd"),
91 + [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
96 + (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
97 + !strconcat(OpcStr, " $rs1, $simm13, $rd"),
98 + [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
108 + (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
109 + !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
113 + (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
114 + !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
[all …]
HDpatch-r262261-llvm-r199977-sparc.diff53 #define JMP_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x38 << 19) \
54 | ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
56 +#define OR_INST_I(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x02 << 19) \
57 + | ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
58 +#define OR_INST_R(rs1, rs2, rd) (0x80000000 | ((rd) << 25) | (0x02 << 19) \
59 + | ((rs1) << 14) | (0 << 13) | ((rs2) & 0x1F))
62 +#define LDX_INST(rs1, imm, rd) (0xC0000000 | ((rd) << 25) | (0x0B << 19) \
63 + | ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
64 +#define SLLX_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x25 << 19) \
65 + | ((rs1) << 14) | (3 << 12) | ((imm) & 0x3F))
[all …]
HDpatch-r262261-llvm-r198286-sparc.diff11 @@ -975,6 +975,33 @@ let rs1 = 0 in
16 +let hasSideEffects =1, rd = 0, rs1 = 0b01111, rs2 = 0 in
19 +let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
36 + (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
38 + "cas [$rs1], $rs2, $rd",
40 + (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
139 + (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
141 + "casx [$rs1], $rs2, $rd",
143 + (atomic_cmp_swap i64:$rs1, i64:$rs2, i64:$swap))]>;
HDpatch-r262261-llvm-r200963-sparc.diff60 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
62 "cas [$rs1], $rs2, $rd",
129 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
131 "casx [$rs1], $rs2, $rd",
HDpatch-r262415-llvm-r201994-sparc.diff15 +let isBarrier = 1, isTerminator = 1, rd = 0b1000, rs1 = 0, simm13 = 5 in
HDpatch-r262261-llvm-r198280-sparc.diff17 let rs1 = 0 in
HDpatch-r262261-llvm-r198157-sparc.diff72 + (ins I64Regs:$rs1, I64Regs:$rs2, TLSSym:$sym),
73 + "add $rs1, $rs2, $rd, $sym",
75 + (tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>;
/trueos/contrib/llvm/lib/Target/Sparc/
HDSparcInstrInfo.td233 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
234 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
235 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
237 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
238 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
239 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
246 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
247 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
249 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
250 !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
[all …]
HDSparcJITInfo.cpp102 #define JMP_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x38 << 19) \ argument
103 | ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
105 #define OR_INST_I(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x02 << 19) \ argument
106 | ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
107 #define OR_INST_R(rs1, rs2, rd) (0x80000000 | ((rd) << 25) | (0x02 << 19) \ argument
108 | ((rs1) << 14) | (0 << 13) | ((rs2) & 0x1F))
111 #define LDX_INST(rs1, imm, rd) (0xC0000000 | ((rd) << 25) | (0x0B << 19) \ argument
112 | ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
113 #define SLLX_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x25 << 19) \ argument
114 | ((rs1) << 14) | (3 << 12) | ((imm) & 0x3F))
[all …]
HDSparcInstr64Bit.td166 (ins I64Regs:$rs1, I64Regs:$rs2, TLSSym:$sym),
167 "add $rs1, $rs2, $rd, $sym",
169 (tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>;
192 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
193 "mulx $rs1, $rs2, $rd",
194 [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
196 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
197 "mulx $rs1, $simm13, $rd",
198 [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>;
203 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
[all …]
HDSparcInstrFormats.td94 bits<5> rs1;
98 let Inst{18-14} = rs1;
149 let rs1 = 0;
199 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
200 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
201 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>;
202 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt),
203 !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
204 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>;
/trueos/sys/sparc64/include/
HDcpufunc.h63 #define casa(rs1, rs2, rd, asi) ({ \ argument
66 : "+r" (__rd), "=m" (*rs1) \
67 : "r" (rs1), "n" (asi), "r" (rs2), "m" (*rs1)); \
71 #define casxa(rs1, rs2, rd, asi) ({ \ argument
74 : "+r" (__rd), "=m" (*rs1) \
75 : "r" (rs1), "n" (asi), "r" (rs2), "m" (*rs1)); \
/trueos/lib/libc/sparc64/fpu/
HDfpu.c273 int opf, rs1, rs2, rd, type, mask, cx, cond; in __fpu_execute() local
285 rs1 = RN_DECODE(type, IF_F3_RS1(insn)); in __fpu_execute()
290 if ((rs1 | rs2 | rd) & opmask[type]) in __fpu_execute()
348 __fpu_explode(fe, &fe->fe_f1, type, rs1); in __fpu_execute()
353 __fpu_explode(fe, &fe->fe_f1, type, rs1); in __fpu_execute()
371 __fpu_explode(fe, &fe->fe_f1, type, rs1); in __fpu_execute()
376 __fpu_explode(fe, &fe->fe_f1, type, rs1); in __fpu_execute()
381 __fpu_explode(fe, &fe->fe_f1, type, rs1); in __fpu_execute()
386 __fpu_explode(fe, &fe->fe_f1, type, rs1); in __fpu_execute()
394 __fpu_explode(fe, &fe->fe_f1, type, rs1); in __fpu_execute()
/trueos/crypto/openssl/crypto/sha/asm/
HDsha1-sparcv9a.pl551 my ($mnemonic,$rs1,$rs2,$rd)=@_;
559 $ref = "$mnemonic\t$rs1,$rs2,$rd";
562 foreach ($rs1,$rs2,$rd) {
573 0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
580 my ($mnemonic,$rs1,$rs2,$rd)=@_;
582 my $ref="$mnemonic\t$rs1,$rs2,$rd";
584 foreach ($rs1,$rs2,$rd) {
589 0x81b00300|$rd<<25|$rs1<<14|$rs2,
/trueos/contrib/netbsd-tests/lib/libcurses/
HDatf.terminfo37 rmm=rmm, rmso=rmso, rmul=rmul, rs1=rs1,
/trueos/contrib/gcc/config/sparc/
HDsparc.c2886 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL; in legitimate_address_p() local
2889 rs1 = addr; in legitimate_address_p()
2892 rs1 = XEXP (addr, 0); in legitimate_address_p()
2897 if (!REG_P (rs1) in legitimate_address_p()
2898 && GET_CODE (rs1) != SUBREG in legitimate_address_p()
2901 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM))) in legitimate_address_p()
2903 rs1 = XEXP (addr, 1); in legitimate_address_p()
2908 && rs1 == pic_offset_table_rtx in legitimate_address_p()
2916 || ((REG_P (rs1) in legitimate_address_p()
2917 || GET_CODE (rs1) == SUBREG) in legitimate_address_p()
[all …]
/trueos/sys/gnu/dts/arm/
HDxenvm-4.2.dts79 arm,v2m-memory-map = "rs1";
HDvexpress-v2m.dtsi13 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
17 * CHANGES TO vexpress-v2m-rs1.dtsi!
HDvexpress-v2p-ca5s.dts251 /include/ "vexpress-v2m-rs1.dtsi"
HDvexpress-v2p-ca15-tc1.dts281 /include/ "vexpress-v2m-rs1.dtsi"
/trueos/sys/cddl/contrib/opensolaris/uts/sparc/dtrace/
HDfasttrap_isa.c906 uint_t rs1 = RS1(tp->ftt_instr); in fasttrap_pid_probe() local
911 npc = fasttrap_getreg(rp, rs1) + imm; in fasttrap_pid_probe()
913 uint_t rs1 = RS1(tp->ftt_instr); in fasttrap_pid_probe() local
916 npc = fasttrap_getreg(rp, rs1) + in fasttrap_pid_probe()
/trueos/sys/dev/isp/
HDisp.c3502 sns_gid_ft_rsp_t *rs0, *rs1; in isp_scan_fabric() local
3572 rs1 = (sns_gid_ft_rsp_t *) ((uint8_t *)fcp->isp_scratch+OGPOFF); in isp_scan_fabric()
3573 isp_get_gid_ft_response(isp, rs0, rs1, NGENT); in isp_scan_fabric()
3579 if (rs1->snscb_cthdr.ct_cmd_resp != LS_ACC) { in isp_scan_fabric()
3581 if (rs1->snscb_cthdr.ct_reason == 9 && rs1->snscb_cthdr.ct_explanation == 7) { in isp_scan_fabric()
3588 rs1->snscb_cthdr.ct_reason, in isp_scan_fabric()
3589 rs1->snscb_cthdr.ct_explanation); in isp_scan_fabric()
3613 if (rs1->snscb_ports[portidx].control & 0x80) { in isp_scan_fabric()
3621 if ((rs1->snscb_ports[portidx].control & 0x80) == 0) { in isp_scan_fabric()
3633 ((rs1->snscb_ports[portidx].portid[0]) << 16) | in isp_scan_fabric()
[all …]
/trueos/sys/sparc64/sparc64/
HDpmap.c448 #define LDDA_R_I_R(rd, imm_asi, rs1, rs2) \ in pmap_bootstrap() argument
450 EIF_F3_RS1(rs1) | EIF_F3_I(0) | EIF_F3_IMM_ASI(imm_asi) | \ in pmap_bootstrap()
452 #define OR_R_I_R(rd, imm13, rs1) \ in pmap_bootstrap() argument
454 EIF_F3_RS1(rs1) | EIF_F3_I(1) | EIF_IMM(imm13, 13)) in pmap_bootstrap()
458 #define WR_R_I(rd, imm13, rs1) \ in pmap_bootstrap() argument
460 EIF_F3_RS1(rs1) | EIF_F3_I(1) | EIF_IMM(imm13, 13)) in pmap_bootstrap()

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