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Searched refs:rdmsr (Results 1 – 25 of 49) sorted by relevance

12

/trueos/sys/amd64/vmm/intel/
HDvmx_msr.c69 return (rdmsr(MSR_VMX_BASIC) & 0xffffffff); in vmx_revision()
95 if (rdmsr(MSR_VMX_BASIC) & (1UL << 55)) in vmx_set_ctlreg()
100 val = rdmsr(ctl_reg); in vmx_set_ctlreg()
102 trueval = rdmsr(true_ctl_reg); /* step c */ in vmx_set_ctlreg()
243 host_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR); in vmx_msr_init()
244 host_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR); in vmx_msr_init()
245 host_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR); in vmx_msr_init()
246 host_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK); in vmx_msr_init()
251 misc_enable = rdmsr(MSR_IA32_MISC_ENABLE); in vmx_msr_init()
338 guest_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR); in vmx_msr_guest_exit()
[all …]
/trueos/sys/dev/hyperv/vmbus/
HDhv_hv.c79 u_int now = rdmsr(HV_X64_MSR_TIME_REF_COUNT); in hv_get_timecount()
234 hypercall_msr.as_uint64_t = rdmsr(HV_X64_MSR_HYPERCALL); in hv_vmbus_init()
250 hypercall_msr.as_uint64_t = rdmsr(HV_X64_MSR_HYPERCALL); in hv_vmbus_init()
379 version = rdmsr(HV_X64_MSR_SVERSION); in hv_vmbus_synic_init()
390 simp.as_uint64_t = rdmsr(HV_X64_MSR_SIMP); in hv_vmbus_synic_init()
400 siefp.as_uint64_t = rdmsr(HV_X64_MSR_SIEFP); in hv_vmbus_synic_init()
417 sctrl.as_uint64_t = rdmsr(HV_X64_MSR_SCONTROL); in hv_vmbus_synic_init()
428 hv_vcpu_index = rdmsr(HV_X64_MSR_VP_INDEX); in hv_vmbus_synic_init()
446 shared_sint.as_uint64_t = rdmsr( in hv_vmbus_synic_cleanup()
458 simp.as_uint64_t = rdmsr(HV_X64_MSR_SIMP); in hv_vmbus_synic_cleanup()
[all …]
/trueos/sys/x86/x86/
HDmca.c417 status = rdmsr(MSR_MC_STATUS(bank)); in mca_check_status()
426 rec->mr_addr = rdmsr(MSR_MC_ADDR(bank)); in mca_check_status()
429 rec->mr_misc = rdmsr(MSR_MC_MISC(bank)); in mca_check_status()
432 rec->mr_mcg_cap = rdmsr(MSR_MCG_CAP); in mca_check_status()
433 rec->mr_mcg_status = rdmsr(MSR_MCG_STATUS); in mca_check_status()
527 ctl = rdmsr(MSR_MC_CTL2(bank)); in cmci_update()
606 mcg_cap = rdmsr(MSR_MCG_CAP); in mca_scan()
797 ctl = rdmsr(MSR_MC_CTL2(i)); in cmci_monitor()
806 ctl = rdmsr(MSR_MC_CTL2(i)); in cmci_monitor()
817 ctl = rdmsr(MSR_MC_CTL2(i)); in cmci_monitor()
[all …]
HDidentcpu.c1112 rdmsr(0x1002); /* Cyrix CPU generates fault. */ in identblue()
1332 msr = rdmsr(MSR_IA32_MISC_ENABLE); in finishidentcpu()
1603 amd_whcr = rdmsr(0xc0000082); in print_AMD_info()
1615 amd_whcr = rdmsr(0xc0000082); in print_AMD_info()
1860 msr = rdmsr(MSR_VM_CR); in print_svm_info()
1969 val = rdmsr(true_msr); in vmx_settable()
1971 val = rdmsr(msr); in vmx_settable()
1985 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); in print_vmx_info()
1988 basic = rdmsr(MSR_VMX_BASIC); in print_vmx_info()
2129 msr = rdmsr(MSR_VMX_EPT_VPID_CAP); in print_vmx_info()
HDtsc.c204 if (rdmsr(MSR_MPERF) > 0 && rdmsr(MSR_APERF) > 0) in probe_tsc_freq()
242 (rdmsr(0x1203) & 0x100000000ULL) == 0) in probe_tsc_freq()
/trueos/sys/amd64/vmm/amd/
HDsvm_msr.c59 host_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR); in svm_msr_init()
60 host_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR); in svm_msr_init()
61 host_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR); in svm_msr_init()
62 host_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK); in svm_msr_init()
/trueos/sys/i386/i386/
HDinitcpu.c453 fcr = rdmsr(0x0107); in init_winchip()
549 apicbase = rdmsr(MSR_APICBASE); in init_ppro()
566 apicbase = rdmsr(MSR_APICBASE); in ppro_reenable_apic()
589 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3); in init_mendocino()
646 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); in init_via()
661 wrmsr(0x1107, rdmsr(0x1107) | fcr); in init_via()
673 wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL); in init_transmeta()
730 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL); in initializecpu()
774 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000); in initializecpu()
791 msr = rdmsr(MSR_EFER) | EFER_NXE; in initializecpu()
[all …]
HDi686_mem.c179 msrv = rdmsr(msr); in i686_mrfetch()
191 msrv = rdmsr(msr); in i686_mrfetch()
203 msrv = rdmsr(msr); in i686_mrfetch()
218 msrv = rdmsr(msr); in i686_mrfetch()
222 msrv = rdmsr(msr + 1); in i686_mrfetch()
323 wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE); in i686_mrstoreone()
330 omsrv = rdmsr(msr); in i686_mrstoreone()
342 omsrv = rdmsr(msr); in i686_mrstoreone()
354 omsrv = rdmsr(msr); in i686_mrstoreone()
369 omsrv = rdmsr(msr); in i686_mrstoreone()
[all …]
HDgeode.c128 a = rdmsr(0x5140000c); in cs5536_led_func()
215 a = rdmsr(0x5140000d); in cs5536_watchdog()
228 m = rdmsr(0x51400029); in cs5536_watchdog()
351 printf("MFGPT bar: %jx\n", rdmsr(0x5140000d)); in geode_probe()
HDlongrun.c93 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN); in tmx86_get_longrun_mode()
96 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01; in tmx86_get_longrun_mode()
141 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN); in tmx86_set_longrun_mode()
149 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS); in tmx86_set_longrun_mode()
HDk6_mem.c113 reg = rdmsr(UWCCR); in k6_mrinit()
166 reg = rdmsr(UWCCR); in k6_mrset()
HDperfmon.c203 pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL; in perfmon_stop()
220 *val = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL; in perfmon_read()
/trueos/sys/amd64/amd64/
HDamd64_mem.c185 msrv = rdmsr(msr); in amd64_mrfetch()
197 msrv = rdmsr(msr); in amd64_mrfetch()
209 msrv = rdmsr(msr); in amd64_mrfetch()
224 msrv = rdmsr(msr); in amd64_mrfetch()
228 msrv = rdmsr(msr + 1); in amd64_mrfetch()
329 wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE); in amd64_mrstoreone()
336 omsrv = rdmsr(msr); in amd64_mrstoreone()
348 omsrv = rdmsr(msr); in amd64_mrstoreone()
360 omsrv = rdmsr(msr); in amd64_mrstoreone()
375 omsrv = rdmsr(msr); in amd64_mrstoreone()
[all …]
HDinitcpu.c110 wrmsr(0xc0011029, rdmsr(0xc0011029) | 1); in init_amd()
138 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); in init_via()
151 wrmsr(0x1107, rdmsr(0x1107) | (1 << 28)); in init_via()
181 msr = rdmsr(MSR_EFER) | EFER_NXE; in initializecpu()
HDcpu_switch.S371 rdmsr
375 rdmsr
379 rdmsr
383 rdmsr
387 rdmsr
391 rdmsr
395 rdmsr
399 rdmsr
/trueos/sys/x86/cpufreq/
HDhwpstate.c168 msr = rdmsr(MSR_AMD_10H_11H_LIMIT); in hwpstate_goto_pstate()
196 msr = rdmsr(MSR_AMD_10H_11H_STATUS); in hwpstate_goto_pstate()
245 msr = rdmsr(MSR_AMD_10H_11H_STATUS); in hwpstate_get()
369 msr = rdmsr(MSR_AMD_10H_11H_LIMIT); in hwpstate_probe()
407 msr = rdmsr(MSR_AMD_10H_11H_LIMIT); in hwpstate_get_info_from_msr()
411 msr = rdmsr(MSR_AMD_10H_11H_CONFIG + i); in hwpstate_get_info_from_msr()
HDpowernow.c282 status = rdmsr(MSR_AMDK7_FIDVID_STATUS); in pn7_setfidvid()
290 ctl = rdmsr(MSR_AMDK7_FIDVID_CTL) & PN7_CTR_FIDCHRATIO; in pn7_setfidvid()
321 *status = rdmsr(MSR_AMDK7_FIDVID_STATUS); in pn8_read_pending_wait()
491 status = rdmsr(MSR_AMDK7_FIDVID_STATUS); in pn_get()
657 status = rdmsr(MSR_AMDK7_FIDVID_STATUS); in pn_decode_pst()
827 status = rdmsr(MSR_AMDK7_FIDVID_STATUS); in pn_decode_acpi()
895 status = rdmsr(MSR_AMDK7_FIDVID_STATUS); in pn_probe()
HDp4tcc.c284 msr = rdmsr(MSR_THERM_CONTROL); in p4tcc_set()
326 msr = rdmsr(MSR_THERM_CONTROL); in p4tcc_get()
/trueos/sys/amd64/vmm/
HDvmm_host.c50 vmm_host_efer = rdmsr(MSR_EFER); in vmm_host_state_init()
51 vmm_host_pat = rdmsr(MSR_PAT); in vmm_host_state_init()
/trueos/sys/dev/coretemp/
HDcoretemp.c187 msr = rdmsr(MSR_BIOS_SIGN); in coretemp_attach()
210 msr = rdmsr(MSR_IA32_EXT_CONFIG); in coretemp_attach()
325 msr = rdmsr(MSR_THERM_STATUS); in coretemp_get_thermal_msr()
/trueos/sys/dev/hwpmc/
HDhwpmc_piv.c521 #define P4_PMC_IS_STOPPED(cccr) ((rdmsr(cccr) & P4_CCCR_ENABLE) == 0)
663 rdmsr(P4_CCCR_MSR_FIRST + i) & ~P4_CCCR_ENABLE); in p4_pcpu_fini()
710 tmp = rdmsr(p4_pmcdesc[ri].pm_pmc_msr); in p4_read_pmc()
1238 cccrvalue = rdmsr(pd->pm_cccr_msr); in p4_start_pmc()
1256 escrvalue = rdmsr(escrmsr); in p4_start_pmc()
1275 P4_PCPU_HW_VALUE(pc,ri,cpu) = rdmsr(pd->pm_pmc_msr); in p4_start_pmc()
1361 cccrvalue = rdmsr(pd->pm_cccr_msr); in p4_stop_pmc()
1365 escrvalue = rdmsr(escrmsr); in p4_stop_pmc()
1378 tmp = rdmsr(pd->pm_pmc_msr); in p4_stop_pmc()
1480 cccrval = rdmsr(P4_CCCR_MSR_FIRST + ri); in p4_intr()
[all …]
HDhwpmc_core.c181 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; in core_pcpu_fini()
186 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; in core_pcpu_fini()
410 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; in iaf_start_pmc()
416 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; in iaf_start_pmc()
422 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), in iaf_start_pmc()
423 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); in iaf_start_pmc()
453 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; in iaf_stop_pmc()
459 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; in iaf_stop_pmc()
465 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), in iaf_stop_pmc()
466 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); in iaf_stop_pmc()
[all …]
HDhwpmc_amd.h79 #define AMD_PMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_ENABLE) == 0)
/trueos/sys/dev/agp/
HDagp_nvidia.c396 base = rdmsr(IORR_BASE0 + 2 * iorr_addr); in nvidia_init_iorr()
397 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr); in nvidia_init_iorr()
417 sys = rdmsr(SYSCFG); in nvidia_init_iorr()
/trueos/sys/boot/i386/libi386/
HDamd64_tramp.S81 rdmsr

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