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Searched refs:nae_base (Results 1 – 7 of 7) sorted by relevance

/trueos/sys/mips/nlm/dev/net/
HDnae.c47 nlm_nae_flush_free_fifo(uint64_t nae_base, int nblocks) in nlm_nae_flush_free_fifo() argument
53 nlm_write_nae_reg(nae_base, NAE_RX_FREE_FIFO_POP, fifo_mask); in nlm_nae_flush_free_fifo()
55 data = nlm_read_nae_reg(nae_base, NAE_RX_FREE_FIFO_POP); in nlm_nae_flush_free_fifo()
58 nlm_write_nae_reg(nae_base, NAE_RX_FREE_FIFO_POP, 0); in nlm_nae_flush_free_fifo()
62 nlm_program_nae_parser_seq_fifo(uint64_t nae_base, int maxports, in nlm_program_nae_parser_seq_fifo() argument
73 nlm_write_nae_reg(nae_base, NAE_PARSER_SEQ_FIFO_CFG, val); in nlm_program_nae_parser_seq_fifo()
79 nlm_setup_rx_cal_cfg(uint64_t nae_base, int total_num_ports, in nlm_setup_rx_cal_cfg() argument
104 nlm_write_nae_reg(nae_base, in nlm_setup_rx_cal_cfg()
116 nlm_setup_tx_cal_cfg(uint64_t nae_base, int total_num_ports, in nlm_setup_tx_cal_cfg() argument
132 nlm_write_nae_reg(nae_base, NAE_EGR_NIOR_CAL_LEN_REG, tx_slots - 1); in nlm_setup_tx_cal_cfg()
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HDmdio.c45 nlm_int_gmac_mdio_read(uint64_t nae_base, int bus, int block, in nlm_int_gmac_mdio_read() argument
61 mdio_ld_cmd = nlm_read_nae_reg(nae_base, in nlm_int_gmac_mdio_read()
64 nlm_write_nae_reg(nae_base, in nlm_int_gmac_mdio_read()
69 nlm_write_nae_reg(nae_base, in nlm_int_gmac_mdio_read()
74 nlm_write_nae_reg(nae_base, in nlm_int_gmac_mdio_read()
79 while(nlm_read_nae_reg(nae_base, in nlm_int_gmac_mdio_read()
84 nlm_write_nae_reg(nae_base, in nlm_int_gmac_mdio_read()
89 return nlm_read_nae_reg(nae_base, in nlm_int_gmac_mdio_read()
95 nlm_int_gmac_mdio_write(uint64_t nae_base, int bus, int block, in nlm_int_gmac_mdio_write() argument
111 mdio_ld_cmd = nlm_read_nae_reg(nae_base, in nlm_int_gmac_mdio_write()
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HDxaui.c45 nlm_xaui_pcs_init(uint64_t nae_base, int xaui_cplx_mask) in nlm_xaui_pcs_init() argument
64 lane_enable = nlm_read_nae_reg(nae_base, in nlm_xaui_pcs_init()
74 nlm_write_nae_reg(nae_base, in nlm_xaui_pcs_init()
80 lane_enable = nlm_read_nae_reg(nae_base, in nlm_xaui_pcs_init()
90 nlm_write_nae_reg(nae_base, in nlm_xaui_pcs_init()
103 xlp_nae_lane_reset_txpll(nae_base, in nlm_xaui_pcs_init()
106 xlp_ax_nae_lane_reset_txpll(nae_base, block, in nlm_xaui_pcs_init()
122 regval = nlm_read_nae_reg(nae_base, reg); in nlm_xaui_pcs_init()
127 regval = nlm_read_nae_reg(nae_base, reg); in nlm_xaui_pcs_init()
132 regval = nlm_read_nae_reg(nae_base, reg); in nlm_xaui_pcs_init()
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HDsgmii.c43 nlm_configure_sgmii_interface(uint64_t nae_base, int block, int port, in nlm_configure_sgmii_interface() argument
54 nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF1), data1); in nlm_configure_sgmii_interface()
59 nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF2), data2); in nlm_configure_sgmii_interface()
63 nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF1), data1); in nlm_configure_sgmii_interface()
66 nlm_write_nae_reg(nae_base, SGMII_MAX_FRAME(block, port), mtu); in nlm_configure_sgmii_interface()
70 nlm_sgmii_pcs_init(uint64_t nae_base, uint32_t cplx_mask) in nlm_sgmii_pcs_init() argument
72 xlp_nae_config_lane_gmac(nae_base, cplx_mask); in nlm_sgmii_pcs_init()
76 nlm_nae_setup_mac(uint64_t nae_base, int nblock, int iface, int reset, in nlm_nae_setup_mac() argument
81 mac_cfg1 = nlm_read_nae_reg(nae_base, in nlm_nae_setup_mac()
83 mac_cfg2 = nlm_read_nae_reg(nae_base, in nlm_nae_setup_mac()
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HDxlpge.c325 uint64_t nae_base = sc->base; in nlm_setup_interface() local
330 nlm_config_xaui(nae_base, nblock, mtu, in nlm_setup_interface()
332 nlm_config_freein_fifo_uniq_cfg(nae_base, in nlm_setup_interface()
334 nlm_config_ucore_iface_mask_cfg(nae_base, in nlm_setup_interface()
337 nlm_program_flow_cfg(nae_base, port, cur_flow_base, flow_mask); in nlm_setup_interface()
340 nlm_configure_sgmii_interface(nae_base, nblock, port, mtu, 0); in nlm_setup_interface()
344 nlm_nae_init_netior(nae_base, sc->nblocks); in nlm_setup_interface()
345 nlm_nae_open_if(nae_base, nblock, sc->cmplx_type[nblock], port, in nlm_setup_interface()
350 nlm_nae_init_ucore(nae_base, port, ucore_mask); in nlm_setup_interface()
356 uint64_t nae_base; in nlm_setup_interfaces() local
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/trueos/sys/mips/nlm/hal/
HDucore_loader.h43 nlm_ucore_load_image(uint64_t nae_base, int ucore) in nlm_ucore_load_image() argument
45 uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET + in nlm_ucore_load_image()
60 nlm_ucore_write_sharedmem(uint64_t nae_base, int index, uint32_t data) in nlm_ucore_write_sharedmem() argument
63 uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET; in nlm_ucore_write_sharedmem()
68 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG); in nlm_ucore_write_sharedmem()
70 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, in nlm_ucore_write_sharedmem()
76 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg); in nlm_ucore_write_sharedmem()
81 nlm_ucore_read_sharedmem(uint64_t nae_base, int index) in nlm_ucore_read_sharedmem() argument
83 uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET; in nlm_ucore_read_sharedmem()
86 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG); in nlm_ucore_read_sharedmem()
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HDnae.h604 void nlm_nae_flush_free_fifo(uint64_t nae_base, int nblocks);
611 void nlm_setup_poe_class_config(uint64_t nae_base, int max_poe_classes,
630 int nlm_nae_init_netior(uint64_t nae_base, int nblocks);
634 void nlm_nae_init_ucore(uint64_t nae_base, int if_num, uint32_t ucore_mask);