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Searched refs:mmio (Results 1 – 25 of 64) sorted by relevance

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/trueos/sys/mips/rmi/
HDpic.h162 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); in pic_read_control() local
166 reg = xlr_read_reg(mmio, PIC_CTRL); in pic_read_control()
174 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); in pic_write_control() local
177 xlr_write_reg(mmio, PIC_CTRL, control); in pic_write_control()
184 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); in pic_update_control() local
187 xlr_write_reg(mmio, PIC_CTRL, (control | xlr_read_reg(mmio, PIC_CTRL))); in pic_update_control()
194 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); in pic_ack() local
196 xlr_write_reg(mmio, PIC_INT_ACK, 1U << picintr); in pic_ack()
202 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); in pic_send_ipi() local
207 xlr_write_reg(mmio, PIC_IPI, (pid << 20) | (tid << 16) | ipi); in pic_send_ipi()
[all …]
HDxlr_machdep.c307 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); in xlr_pic_init() local
312 xlr_write_reg(mmio, PIC_CTRL, 0); in xlr_pic_init()
322 xlr_write_reg(mmio, PIC_IRT_1(i), (1 << 30) | (1 << 6) | irq); in xlr_pic_init()
324 xlr_write_reg(mmio, PIC_IRT_0(i), 0x01); in xlr_pic_init()
522 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); in platform_reset() local
525 xlr_write_reg(mmio, 8, 1); in platform_reset()
HDboard.c62 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); in xlr_pcmcia_present() local
65 resetconf = xlr_read_reg(mmio, 21); in xlr_pcmcia_present()
276 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); in xls_board_specific_overrides() local
281 tmp = xlr_read_reg(mmio, 35); in xls_board_specific_overrides()
HDiodi.c90 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_FLASH_OFFSET); in bridge_pcmcia_ack() local
92 xlr_write_reg(mmio, 0x60, 0xffffffff); in bridge_pcmcia_ack()
/trueos/sys/mips/rmi/dev/xlr/
HDrge.c636 regval = xlr_read_reg(priv->mmio, R_TX_CONTROL); in rmi_xlr_mac_set_enable()
640 xlr_write_reg(priv->mmio, R_TX_CONTROL, regval); in rmi_xlr_mac_set_enable()
642 regval = xlr_read_reg(priv->mmio, R_RX_CONTROL); in rmi_xlr_mac_set_enable()
646 xlr_write_reg(priv->mmio, R_RX_CONTROL, regval); in rmi_xlr_mac_set_enable()
648 regval = xlr_read_reg(priv->mmio, R_MAC_CONFIG_1); in rmi_xlr_mac_set_enable()
650 xlr_write_reg(priv->mmio, R_MAC_CONFIG_1, regval); in rmi_xlr_mac_set_enable()
652 regval = xlr_read_reg(priv->mmio, R_TX_CONTROL); in rmi_xlr_mac_set_enable()
656 xlr_write_reg(priv->mmio, R_TX_CONTROL, regval); in rmi_xlr_mac_set_enable()
658 regval = xlr_read_reg(priv->mmio, R_RX_CONTROL); in rmi_xlr_mac_set_enable()
660 xlr_write_reg(priv->mmio, R_RX_CONTROL, regval); in rmi_xlr_mac_set_enable()
[all …]
/trueos/sys/dev/drm/
HDsis_drv.h57 #define SIS_BASE (dev_priv->mmio)
62 drm_local_map_t *mmio; member
HDr128_drv.h122 drm_local_map_t *mmio; member
396 #define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
397 #define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
398 #define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
399 #define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
HDmga_drv.h145 drm_local_map_t *mmio; member
203 #define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle))
220 #define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg))
221 #define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg))
222 #define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val))
223 #define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val))
HDvia_map.c53 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); in via_do_init_map()
54 if (!dev_priv->mmio) { in via_do_init_map()
HDvia_drv.h68 drm_local_map_t *mmio; member
111 #define VIA_BASE ((dev_priv->mmio))
HDsavage_drv.h158 drm_local_map_t *mmio; member
491 #define SAVAGE_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
492 #define SAVAGE_WRITE(reg) DRM_WRITE32( dev_priv->mmio, (reg) )
HDradeon_drv.h375 drm_local_map_t *mmio; member
1825 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1829 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \
1831 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \
1832 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \
1835 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1836 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
HDmach64_drv.h110 drm_local_map_t *mmio; member
494 #define MACH64_READ(reg) DRM_READ32(dev_priv->mmio, (reg) )
495 #define MACH64_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio, (reg), (val) )
HDradeon_cp.c111 ret = DRM_READ32(dev_priv->mmio, addr); in RADEON_READ_MM()
113 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr); in RADEON_READ_MM()
114 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA); in RADEON_READ_MM()
1721 if (dev_priv->mmio) /* remove this after permanent addmaps */ in radeon_do_release()
1724 if (dev_priv->mmio) { /* remove all surfaces */ in radeon_do_release()
2036 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio); in radeon_driver_load()
2084 drm_rmmap(dev, dev_priv->mmio); in radeon_driver_unload()
HDmga_dma.c724 _DRM_REGISTERS, _DRM_READ_ONLY, & dev_priv->mmio); in mga_do_dma_bootstrap()
852 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); in mga_do_init_dma()
853 if (!dev_priv->mmio) { in mga_do_init_dma()
996 dev_priv->mmio = NULL; in mga_do_cleanup_dma()
HDvia_dma.c188 if (!dev_priv || !dev_priv->mmio) { in via_initialize()
232 (volatile uint32_t *)((char *)dev_priv->mmio->virtual + in via_initialize()
HDr128_cce.c469 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); in r128_do_init_cce()
470 if (!dev_priv->mmio) { in r128_do_init_cce()
/trueos/sys/amd64/vmm/io/
HDppt.c83 struct vm_memory_segment mmio[MAX_MMIOSEGS]; member
202 seg = &ppt->mmio[i]; in ppt_unmap_mmio()
323 seg = &ppt->mmio[i]; in ppt_is_mmio()
410 seg = &ppt->mmio[i]; in ppt_map_mmio()
/trueos/sys/dev/drm2/i915/
HDintel_ringbuffer.c767 uint32_t mmio = 0; in intel_ring_setup_status_page() local
775 mmio = RENDER_HWS_PGA_GEN7; in intel_ring_setup_status_page()
778 mmio = BLT_HWS_PGA_GEN7; in intel_ring_setup_status_page()
781 mmio = BSD_HWS_PGA_GEN7; in intel_ring_setup_status_page()
785 mmio = RING_HWS_PGA_GEN6(ring->mmio_base); in intel_ring_setup_status_page()
787 mmio = RING_HWS_PGA(ring->mmio_base); in intel_ring_setup_status_page()
790 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); in intel_ring_setup_status_page()
791 POSTING_READ(mmio); in intel_ring_setup_status_page()
/trueos/sys/gnu/dts/arm/
HDat91sam9g20.dtsi24 compatible = "mmio-sram";
HDimx6dl.dtsi64 compatible = "mmio-sram";
HDat91sam9xe.dtsi57 compatible = "mmio-sram";
HDexynos5410.dtsi135 compatible = "mmio-sram";
/trueos/sys/dev/drm2/radeon/
HDradeon_drv.h281 drm_local_map_t *mmio; member
1854 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1858 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \
1860 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \
1861 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \
1864 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1865 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
/trueos/sys/mips/rmi/dev/nlge/
HDif_nlge.c2184 xlr_reg_t *mmio; in nlge_gmac_config_speed() local
2201 mmio = sc->base; in nlge_gmac_config_speed()
2226 NLGE_WRITE(mmio, R_INTERFACE_CONTROL, sgmii_speed[sc->speed]); in nlge_gmac_config_speed()
2229 NLGE_WRITE(mmio, R_MAC_CONFIG_2, 0x7117); in nlge_gmac_config_speed()
2231 NLGE_WRITE(mmio, R_MAC_CONFIG_2, 0x7217); in nlge_gmac_config_speed()
2237 NLGE_WRITE(mmio, R_CORECONTROL, core_ctl[sc->speed]); in nlge_gmac_config_speed()

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