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Searched refs:mBIT (Results 1 – 17 of 17) sorted by relevance

/trueos/sys/dev/vxge/vxgehal/
HDvxgehal-vpath-reg.h47 #define VXGE_HAL_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT mBIT(1)
52 #define VXGE_HAL_PRC_ALARM_REG_PRC_RING_BUMP mBIT(0)
53 #define VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ERR mBIT(1)
54 #define VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT mBIT(2)
55 #define VXGE_HAL_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR mBIT(3)
60 #define VXGE_HAL_PRC_CFG1_TIM_RING_BUMP_INT_ENABLE mBIT(34)
61 #define VXGE_HAL_PRC_CFG1_RTI_TINT_DISABLE mBIT(35)
62 #define VXGE_HAL_PRC_CFG1_GREEDY_RETURN mBIT(36)
63 #define VXGE_HAL_PRC_CFG1_QUICK_SHOT mBIT(37)
64 #define VXGE_HAL_PRC_CFG1_RX_TIMER_CI mBIT(39)
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HDvxgehal-srpcim-reg.h46 #define VXGE_HAL_SRPCIM_PCIPIF_INT_STATUS_MRPCIM_MSG_INT mBIT(3)
47 #define VXGE_HAL_SRPCIM_PCIPIF_INT_STATUS_VPATH_MSG_VPATH_MSG_INT mBIT(7)
49 mBIT(11)
52 #define VXGE_HAL_MRPCIM_MSG_REG_SWIF_MRPCIM_TO_SRPCIM_RMSG_INT mBIT(3)
56 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH0_TO_SRPCIM_RMSG_INT mBIT(0)
57 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH1_TO_SRPCIM_RMSG_INT mBIT(1)
58 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH2_TO_SRPCIM_RMSG_INT mBIT(2)
59 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH3_TO_SRPCIM_RMSG_INT mBIT(3)
60 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH4_TO_SRPCIM_RMSG_INT mBIT(4)
61 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH5_TO_SRPCIM_RMSG_INT mBIT(5)
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HDvxgehal-vpmgmt-reg.h41 #define VXGE_HAL_ONE_CFG_SR_RDY_ONE_CFG_SR_RDY mBIT(7)
50 #define VXGE_HAL_VPATH_IS_FIRST_VPATH_IS_FIRST mBIT(3)
55 #define VXGE_HAL_SRPCIM_TO_VPATH_WMSG_TRIG_TRIG mBIT(0)
71 #define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_IGNORE_FRAME_ERR mBIT(3)
72 #define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SUPPORT_SNAP_AB_N mBIT(7)
73 #define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SEARCH_FOR_HAO mBIT(18)
75 mBIT(19)
76 #define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_IPV6_STOP_SEARCHING mBIT(23)
77 #define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_NO_PS_IF_UNKNOWN mBIT(27)
78 #define VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SEARCH_FOR_ETYPE mBIT(35)
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HDvxgehal-mrpcim-reg.h41 #define VXGE_HAL_G3FBCT_INT_STATUS_ERR_G3IF_INT mBIT(0)
44 #define VXGE_HAL_G3FBCT_ERR_REG_G3IF_SM_ERR mBIT(4)
45 #define VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_DECC mBIT(5)
46 #define VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_U_DECC mBIT(6)
47 #define VXGE_HAL_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_DECC mBIT(7)
48 #define VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_SECC mBIT(29)
49 #define VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_U_SECC mBIT(30)
50 #define VXGE_HAL_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_SECC mBIT(31)
63 #define VXGE_HAL_G3FBCT_CONFIG1_BIC_OFF mBIT(15)
64 #define VXGE_HAL_G3FBCT_CONFIG1_IGNORE_BEM mBIT(23)
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HDvxgehal-common-reg.h43 #define VXGE_HAL_PRC_STATUS1_PRC_VP_QUIESCENT(n) mBIT(n)
45 #define VXGE_HAL_RXDCM_RESET_IN_PROGRESS_PRC_VP(n) mBIT(n)
47 #define VXGE_HAL_REPLICQ_FLUSH_IN_PROGRESS_NOA_VP(n) mBIT(n)
49 #define VXGE_HAL_RXPE_CMDS_RESET_IN_PROGRESS_NOA_VP(n) mBIT(n)
51 #define VXGE_HAL_MXP_CMDS_RESET_IN_PROGRESS_NOA_VP(n) mBIT(n)
53 #define VXGE_HAL_NOFFLOAD_RESET_IN_PROGRESS_PRC_VP(n) mBIT(n)
55 #define VXGE_HAL_RD_REQ_IN_PROGRESS_VP(n) mBIT(n)
57 #define VXGE_HAL_RD_REQ_OUTSTANDING_VP(n) mBIT(n)
59 #define VXGE_HAL_KDFC_RESET_IN_PROGRESS_NOA_VP(n) mBIT(n)
63 #define VXGE_HAL_ONE_CFG_VP_RDY(n) mBIT(n)
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HDvxgehal-regdefs.h75 #define VXGE_HAL_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN mBIT(3)
76 #define VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE mBIT(19)
77 #define VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH mBIT(23)
78 #define VXGE_HAL_TXMAC_GEN_CFG1_HOST_APPEND_FCS mBIT(31)
156 #define VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_PRIVILEGED_MODE mBIT(54)
207 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_STREAM_SKIP mBIT(63)
240 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_SRC_DEST_SEL mBIT(3)
242 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_TCP_UDP_SEL mBIT(7)
247 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN mBIT(3)
259 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN mBIT(15)
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HDvxgehal-device.c103 if (!(hldev->vpath_assignments & mBIT(i))) in vxge_hal_device_pciconfig_get()
763 if (!(hldev->vpath_assignments & mBIT(i))) in __hal_device_host_info_get()
979 if (!(hldev->vpaths_deployed & mBIT(i))) in vxge_hal_device_reset()
1032 if (!(hldev->vpaths_deployed & mBIT(i))) in vxge_hal_device_reset_poll()
1106 if (!(hldev->vpaths_deployed & mBIT(i))) in vxge_hal_device_mrpcim_reset_poll()
1349 if (!(hldev->vpaths_deployed & mBIT(i))) in vxge_hal_device_intr_enable()
1460 if (!(hldev->vpaths_deployed & mBIT(i))) in vxge_hal_device_intr_disable()
1642 if (!(hldev->vpaths_deployed & mBIT(i))) in vxge_hal_device_begin_irq()
1701 if (!(hldev->vpaths_deployed & mBIT(i))) in vxge_hal_device_continue_irq()
1885 if (!(hldev->vpath_assignments & mBIT(i))) in vxge_hal_device_link_state_test()
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HDvxgehal-mgmt.c1223 (!(hldev->vpath_assignments & mBIT(vp_id)))) { in vxge_hal_mgmt_reg_read()
1237 (!(hldev->vpath_assignments & mBIT(vp_id)))) { in vxge_hal_mgmt_reg_read()
1410 (!(hldev->vpath_assignments & mBIT(vp_id)))) { in vxge_hal_mgmt_reg_write()
1425 (!(hldev->vpath_assignments & mBIT(vp_id)))) { in vxge_hal_mgmt_reg_write()
1804 (!(hldev->vpath_assignments & mBIT(vp_id)))) { in vxge_hal_mgmt_register_config()
1827 (!(hldev->vpath_assignments & mBIT(vp_id)))) { in vxge_hal_mgmt_register_config()
HDvxgehal-ifmsg.c59 mBIT((u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_SRC(wmsg)))) { in __hal_ifmsg_wmsg_process()
HDvxgehal-virtualpath.c734 val64 |= mBIT(i); in __hal_vpath_vpath_map_get()
7085 if (!(hldev->vpath_assignments & mBIT(j))) in vxge_hal_vpath_msix_set()
7194 (u32) bVAL32(mBIT(hldev->msix_map[msix_id].vp_id), 0), in vxge_hal_vpath_msix_mask()
7240 (u32) bVAL32(mBIT(hldev->msix_map[msix_id].vp_id), 0), in vxge_hal_vpath_msix_clear()
7256 (u32) bVAL32(mBIT(hldev->msix_map[msix_id].vp_id), 0), in vxge_hal_vpath_msix_clear()
7355 vp->vpath->hldev->header.regh0, (u32) bVAL32(mBIT(msix_id >> 2), 0), in vxge_hal_vpath_mf_msix_mask()
7390 (u32) bVAL32(mBIT((msix_id >> 2)), 0), in vxge_hal_vpath_mf_msix_clear()
7395 (u32) bVAL32(mBIT((msix_id >> 2)), 0), in vxge_hal_vpath_mf_msix_clear()
7418 (u32) bVAL32(mBIT(msix_id >> 2), 0), in vxge_hal_vpath_mf_msix_unmask()
7458 (u32) bVAL32(mBIT(hldev->msix_map[msix_id].vp_id), 0), in vxge_hal_vpath_msix_unmask()
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HDvxgehal-srpcim.c205 if (val64 & mBIT(i)) { in vxge_hal_srpcim_alarm_process()
HDvxgehal-mgmtaux.c701 if (!(((__hal_device_t *) hldev)->vpath_assignments & mBIT(i))) in vxge_hal_aux_device_config_read()
1236 if (!(hldev->vpaths_deployed & mBIT(i))) in vxge_hal_aux_stats_device_hw_read()
1578 if (!(hldev->vpaths_deployed & mBIT(i))) in vxge_hal_aux_stats_device_sw_read()
HDvxgehal-mrpcim.c284 if (!((vpath_mask) & mBIT(i))) in vxge_hal_mrpcim_fw_upgrade()
3713 if (!(hldev->vpaths_deployed & mBIT(i))) in vxge_hal_mrpcim_stats_clear()
/trueos/sys/dev/vxge/include/
HDvxgehal-ll.h528 #define VXGE_HAL_RING_RXD_LIST_OWN_ADAPTER mBIT(7)
531 #define VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE mBIT(8)
534 #define VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT mBIT(9)
537 #define VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT mBIT(10)
562 #define VXGE_HAL_RING_RXD_SYN mBIT(16)
565 #define VXGE_HAL_RING_RXD_IS_ICMP mBIT(17)
568 #define VXGE_HAL_RING_RXD_RTH_SPDM_HIT mBIT(18)
571 #define VXGE_HAL_RING_RXD_RTH_IT_HIT mBIT(19)
593 #define VXGE_HAL_RING_RXD_IS_VLAN mBIT(24)
603 #define VXGE_HAL_RING_RXD_IS_IPV4 mBIT(27)
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HDvxge-defs.h57 #define mBIT(loc) (0x8000000000000000ULL >> (loc)) macro
HDvxgehal-config.h1168 #define VXGE_HAL_LAG_DISTRIB_DEST_VPATH_TO_PORT_PORT1(vpid) mBIT(vpid)
1639 #define VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_EN_ENABLE(vpid) mBIT(vpid)
1643 #define VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_PORT1(vpid) mBIT(vpid)
/trueos/sys/dev/vxge/
HDvxge.c3059 if (!((vpath_mask) & mBIT(i))) in vxge_device_hw_info_get()