Searched refs:isZExt (Results 1 – 19 of 19) sorted by relevance
| /trueos/contrib/llvm/lib/Target/ARM/ |
| HD | ARMFastISel.cpp | 184 bool isZExt);
186 unsigned Alignment = 0, bool isZExt = true,
195 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1048 unsigned Alignment, bool isZExt, bool allocReg) { in ARMEmitLoad() argument
1060 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8; in ARMEmitLoad()
1062 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12; in ARMEmitLoad()
1064 if (isZExt) { in ARMEmitLoad()
1079 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8; in ARMEmitLoad()
1081 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12; in ARMEmitLoad()
1083 Opc = isZExt ? ARM::LDRH : ARM::LDRSH; in ARMEmitLoad()
[all …]
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| HD | ARMISelLowering.cpp | 5993 Entry.isZExt = false; in LowerFSINCOS()
6000 Entry.isZExt = false; in LowerFSINCOS()
11089 Entry.isZExt = !isSigned; in LowerDivRem()
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| /trueos/contrib/llvm/include/llvm/Target/ |
| HD | TargetCallingConv.h | 56 bool isZExt() const { return Flags & ZExt; } in isZExt() function
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| HD | TargetLowering.h | 1929 bool isZExt : 1; member
1937 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), in ArgListEntry()
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| /trueos/contrib/llvm/lib/Target/SystemZ/ |
| HD | SystemZCallingConv.td | 13 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
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| /trueos/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | LegalizeDAG.cpp | 1892 Entry.isZExt = !isSigned; in ExpandLibCall()
1941 Entry.isZExt = !isSigned; in ExpandLibCall()
1975 Entry.isZExt = !isSigned; in ExpandChainLibCall()
2103 Entry.isZExt = !isSigned; in ExpandDivRemLibCall()
2112 Entry.isZExt = !isSigned; in ExpandDivRemLibCall()
2210 Entry.isZExt = false; in ExpandSinCosLibCall()
2218 Entry.isZExt = false; in ExpandSinCosLibCall()
2226 Entry.isZExt = false; in ExpandSinCosLibCall()
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| HD | LegalizeTypes.cpp | 1045 Entry.isZExt = !isSigned; in ExpandChainLibCall()
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| HD | TargetLowering.cpp | 72 isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt); in setAttributes()
98 Entry.isZExt = !isSigned; in makeLibCall()
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| HD | SelectionDAGBuilder.cpp | 5387 Entry.isZExt = false; in LowerCallTo()
7038 if (Args[i].isZExt) in LowerCallTo()
7071 else if (Args[i].isZExt) in LowerCallTo()
7090 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt)) in LowerCallTo()
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| HD | LegalizeIntegerTypes.cpp | 2343 Entry.isZExt = false; in ExpandIntRes_XMULO()
2351 Entry.isZExt = false; in ExpandIntRes_XMULO()
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| /trueos/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonISelLowering.cpp | 123 else if (ArgFlags.isZExt()) in CC_Hexagon_VarArg()
161 else if (ArgFlags.isZExt()) in CC_Hexagon()
236 else if (ArgFlags.isZExt()) in RetCC_Hexagon()
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| /trueos/contrib/llvm/lib/Target/X86/ |
| HD | X86FastISel.cpp | 844 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in X86SelectRet()
855 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : in X86SelectRet()
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| HD | X86ISelLowering.cpp | 13363 Entry.isZExt = false; in LowerFSINCOS()
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| /trueos/contrib/llvm/lib/Target/MSP430/ |
| HD | MSP430ISelLowering.cpp | 315 else if (ArgFlags.isZExt()) in AnalyzeArguments()
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| /trueos/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCFastISel.cpp | 146 bool isZExt, unsigned DestReg);
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| HD | PPCISelLowering.cpp | 2181 else if (Flags.isZExt()) in extendArgForPPC64()
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| /trueos/contrib/llvm/lib/Target/NVPTX/ |
| HD | NVPTXISelLowering.cpp | 780 if (Outs[OIdx].Flags.isZExt()) in LowerCall()
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| /trueos/contrib/llvm/lib/Target/Mips/ |
| HD | MipsISelLowering.cpp | 2142 else if (ArgFlags.isZExt()) in CC_MipsO32()
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| /trueos/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelLowering.cpp | 2016 Entry.isZExt = false; in LowerF128ToCall()
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